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2004

A Low Complexity Fetch Architecture for High Performance Superscalar Processors

ACM Transactions on Architecture and Compiler Optimizations (TACO)

M. Valero, O. J. Santana, A. Ramirez, and J. Lluis Larriba-Pey
Predictable Performance in SMT Processors

Computing Frontiers (CF'04)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Limits on Early Release of Physical Registers

J. J. Alastruey, T. Monreal, V. Viñals, and M. Valero
Aggressive Speculative Execution for Hidding Memory Latency

A. Pajuelo, A. González, and M. Valero
Scalability and Complexity of 2-Dimensional SIMD Extensions

XV Jornadas de Paralelismo

M. Álvarez, F. Sánchez, E. Salami, A. Ramirez, and M. Valero
Analysis of Traffic Traces for Statefull Applications

J. Verdú, J. García, M. Nemirovsky, and M. Valero
Selecting Where to Simulate SPEC2000 Using Streams Analysis

XV Jornadas de Paralelismo

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
Stream Predictor Guided Instruction Decoding

XV Jornadas de Paralelismo

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
Throughput versus Quality of Service in SMT processors

Euromicro-DSD (Digital System Design)

E. Fernández, F. Cazorla, A. Ramirez, P. Knijnenburg, R. Sakellariou, and M. Valero
Speculative Execution for Hiding Memory Latency

A. Pajuelo, A. González, and M. Valero

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