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2004

Traffic Aggregation Impact on the Memory Performance of Networking Applications

J. Verdú, M. Nemirovsky, J. García, and M. Valero
Analysis of Traffic Traces for Stateful Applications

J. Verdú, J. García, M. Nemirovsky, and M. Valero
Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers

M. March, J. García, L.. Cerdá, and M. Valero
A Hybrid DRAM/SRAM Design for Fast Packet Buffers

J. García, M. March, L.. Cerdá, J. Corbal, and M. Valero
Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
DCache Warn: An I-Fetch Policy To Increase SMT Efficiency

18th International Parallel and Distributed Processing Symposium (IPDPS-2004)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
Dynamically Controlled Resource Allocation in SMT Processors

37th Annual International Symposium on Microarchitecture (MICRO-37)

F. Cazorla, A. Ramirez, M. Valero, and E. Fernández
QoS for High-Performance SMT Processors in Embedded Systems

IEEE Micro

F. Cazorla, A. Ramirez, M. Valero, P. Knijnenburg, R. Sakellariou, and E. Fernández
A Low Complexity Fetch Architecture for High Performance Superscalar Processors

ACM Transactions on Architecture and Compiler Optimizations (TACO)

M. Valero, O. J. Santana, A. Ramirez, and J. Lluis Larriba-Pey
Predictable Performance in SMT Processors

Computing Frontiers (CF'04)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero

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