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Mostrant 1 - 10 resultats de 19

2009

DIA: A Complexity-Effective Decoding Architecture

IEEE Transactions on Computers

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero

2006

Branch Predictor Guided Instruction Decoding

IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006)

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero

2005

Complexity-Effectiveness in Multithreading Architectures

In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005)

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture

XVI Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
Effective Instruction Prefetching via Fetch Prestaging

IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium

A. Falcón, A. Ramirez, and M. Valero
A Complexity-Effective Simultaneous Multithreading Architecture

34th International Conference on Parallel Processing (ICPP 2005)

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
Better branch prediction through prophet/critic hybrids

IEEE Micro

A. Falcón, J. Stark, A. Ramirez, K. Lai, and M. Valero

2004

Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
Selecting Where to Simulate SPEC2000 Using Streams Analysis

XV Jornadas de Paralelismo

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
Stream Predictor Guided Instruction Decoding

XV Jornadas de Paralelismo

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero

Pàgines