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2015

IEC-61508 SIL 3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis

18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal

I. Agirre, M. Azkarate-askasua, J. Perez, C. Hernández, J. Abella, T. Vardanega, and F. Cazorla
A safety concept for a railway mixed-criticality embedded system based on multicore partitioning

13th IEEE International Conference on Dependable, Autonomic and Secure Computing (DASC-2015)

I. Agirre, M. Azkarate-askasua, A. Larrucea, J. Perez, T. Vardanega, and F. Cazorla
EPC: Extended Path Coverage for Measurement-based Probabilistic Timing Analysis

IEEE Real-Time Systems Symposium (RTSS) San Antonio, Texas

M. Ziccardi, E. Mezzetti, T. Vardanega, J. Abella, and F. Cazorla
Increasing Confidence on Measurement-Based Contention Bounds for Real-Time Round-Robin Buses

Design Automation Conference (DAC) San Francisco, CA

G. Fernandez, J. Jalle, J. Abella, E. Quinones, T. Vardanega, and F. Cazorla
Resource Usage Templates and Signatures for COTS Multicore Processors

DAC '15 Proceedings of the 52nd Annual Design Automation Conference

G. Fernandez, J. Jalle, J. Abella, E. Quinones, T. Vardanega, and F. Cazorla
Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

IEEE 18th International Symposium on Real-Time Distributed Computing, (ISORC)

G. Fernandez, J. Abella, E. Quinones, L. Fossati, M. Zulianello, T. Vardanega, and F. Cazorla
Introduction to Partial Time Composability for COTS Multicores

SAC '15 Proceedings of the 30th Annual ACM Symposium on Applied Computing

G. Fernandez, J. Abella, E. Quinones, L. Fossati, M. Zulianello, T. Vardanega, and F. Cazorla
Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms

DATE '15 Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

F. Wartel, L. Kosmidis, A. Gogonel, A. Baldovin, Z. Stephenson, B. Triquet, E. Quinones, C. Lo, E. Mezzetti, I. Broster, J. Abella, L. Cucu-Grosjean, T. Vardanega, and F. Cazorla

2014

Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture

17th Euromicro Conference on Digital System Design (DSD)

L. Kosmidis, E. Quinones, J. Abella, T. Vardanega, I. Broster, and F. Cazorla
Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art

14th International Workshop on Worst-Case Execution Time Analysis

G. Fernandez, J. Abella, E. Quinones, C. Rochange, T. Vardanega, and F. Cazorla

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