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2018

ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks

2018 IEEE International Symposium on Workload Characterization (IISWC)

C. Bulla, L. Alvarez, M. Moreto, R. Bertran, A. Buyuktosunoglu, and P. Bose
Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs

Proceedings of the 2018 International Conference on Supercomputing - ICS '18

L. Alvarez, M. Casas, J. Labarta, E. Ayguadé, M. Valero, and M. Moreto
Runtime-assisted Cache Coherence Deactivation in Task Parallel Programs

Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC)

P. Caheny, L. Alvarez, M. Valero, M. Moreto, and M. Casas
Architectural Support for Task Dependence Management with Flexible Software Scheduling

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)

E. Castillo, L. Alvarez, M. Moreto, M. Casas, E. Vallejo, J. Luis Bosque, R. Beivide, and M. Valero

2017

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

IEEE Transactions on Parallel and Distributed Systems

P. Caheny, L. Alvarez, S. Derradji, M. Valero, M. Moreto, and M. Casas

2016

CATA: Criticality Aware Task Acceleration for Multicore Processors

2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

E. Castillo, M. Moreto, M. Casas, L. Alvarez, E. Vallejo, K. Chronaki, R. M. Badia, J. Luis Bosque, R. Beivide, E. Ayguade, J. Labarta, and M. Valero

2015

Transparent Management of Scratchpad Memories in Shared Memory Programming Models

L. Alvarez
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

2015 International Conference on Parallel Architecture and Compilation (PACT)

L. Alvarez, M. Moreto, M. Casas, E. Castillo, X. Martorell, J. Labarta, E. Ayguade, and M. Valero
Coherence Protocol for Transparent Management of Scratchpad Memories in Shared Memory Manycore Architectures

Proceedings of the 42nd International Symposium on Computer Architecture (ISCA)

L. Alvarez, L. Vilanova, M. Moreto, M. Casas, M. González, X. Martorell, N. Navarro, E. Ayguade, and M. Valero
Hardware–Software Coherence Protocol for the Coexistence of Caches and Local Memories

IEEE Transactions On Computers

L. Alvarez, L. Vilanova, M. González, X. Martorell, N. Navarro, and E. Ayguade

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