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2003

Deriving analytical models from a limited number of runs

R. M. Badia, G. Rodríguez, and J. Labarta
Performance Analysis of Multilevel Parallel Applications on Shared Memory Architectures

G. Jost, H. Jin, J. Labarta, J. Giménez, and J. J. Caubet
Dimemas: Predicting MPI applications behaviour in Grid environments

R. M. Badia, J. Labarta, J. Giménez, and F. Escalé
Interfacing Computer Aided Parallelization and Performance Analysis

G. Jost, H. Jin, J. Labarta, and J. Giménez
A Framework for Practical Applications Performance Modeling

A. Snavely, L. Carrington, N. Wolter, and J. Labarta
Tolerating branch predictor latency on SMT

5th International Symposium on High Performance Computing (ISHPC-V)

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
An Analysis of Dynamic Instruction Streams

XIV Jornadas de Paralelismo

O. J. Santana, M. Galluzzi, A. Ramirez, and M. Valero
Latency Tolerant Branch Predictors

2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03)

O. J. Santana, A. Ramirez, and M. Valero
Improving Memory Latency Aware Fetch Policies for SMT Processors

5th International Symposium on High Performance Computing (ISHPC-V)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era

Workshop on Complexity-Effective Design (WCED 2003)

C. Acosta, S. Vajapeyam, A. Ramirez, and M. Valero

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