BSC Training Course: RISC-V principles for understanding how to freely develop new solutions
Data: 11/Nov/2024 Time: 09:30 - 13/Nov/2024 Time: 17:30
C6-E101, UPC Campus Nord, Barcelona
Target group: Level: (All courses are designed for specialists with at least 1st cycle degree or similar background experience) Intermediate: Trainees from microelectronic, computer architecture, informatic engineering (or similar), Master Students (MIRI,...), PhD students
Cost: There is no registration fee.
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Sessions will be in November 11th-13th, 2024 from 11:00 – 13:00 and from 14:00 to 17:30 CET with 30’ break in between sessions and 1h lunch break
Agenda still subject to changes
- Day 1: RISC-V Fundamentals & OS
11.00 - 13.00 RISC-V ecosystem and ISA Basics / RISC-V@BSC / structure of the course
13.00 - 14.00 Lunch Break
14.00 - 15.30 Booting a RISC-V compliant OS using QEMU
15.30 - 16:00 Afternoon Break
16.00 – 17:30 Hands-on
- Day 2: RISC-V virtualization and emulation using QEMU
09.00 - 11.00 Virtualization for cloud
11.00 - 11.30 Morning Break
11.30 - 13.00 hands-on
13:00 – 14:00 Lunch Break
14.00 - 15.30 The potential of custom instructions
15.30 - 16:00 Afternoon Break
16.00 – 17:30 Hands-on
- Day 3: RISC-V Vector Extension
09.00 - 11.00 Intro to RVV extension
11.00 - 11.30 Morning Break
11.30 - 13.00 Exploiting RVV with the compiler
13.00 - 14.00 Lunch Break
14.00 - 15.30 Hands-on
15.30 - 16:00 Afternoon Break
16.00 – 17:30 Hands-on
END OF TRAINING COURSE