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2001

Instruction Fetch Architectures and Code Layout Optimizations

Proceedings of the IEEE

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Efficient Execution of Parallel Java Applications

3rd Annual Workshop on Java for High Performance Computing

J. Guitart, X. Martorell, J. Torres, and E. Ayguade
Performance Analysis of Parallel Java Applications on Shared-memory Systems

30th International Conference on Parallel Processing (ICPP'01)

J. Guitart, J. Torres, E. Ayguade, and M. Bull
Strategies for Efficient Exploitation of Loop-Level Parallelism in Java Concurrency and Computation

Concurrency and Computation: Practice and Experience

J. Oliver, J. Guitart, E. Ayguade, N. Navarro, and J. Torres

2000

A Stream Processor Front-end

IEEE Technical Committee on Computer Architecture Newsletter

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
The Effect of Code Reordering on Branch Prediction

International Conference on Parallel Architectures and Compilation Techniques (PACT 2000)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
On the Performance of Fetch Engines Running DSS Workloads

6th International Euro-Par Conference (EuroPar'2000)

C. Navarro, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Fetch Engines and Databases

3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3)

C. Navarro, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Semi-static Branch Prediction for Optimized Code Layouts

3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Trace Cache Redundancy: Red & Blue Traces

Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero

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