SOFTWARE & HARDWARE Licensable technology created by BSC

This technology implements a Post-Quantum Cryptographic (PQC) accelerator to integrate it inside a System On Chip (SoC) for FPGA. The module, implemented in a High-Level Synthesis (HLS) approach, accelerates two PQC schemes, the CRYSTALS-Kyber and the CRYSTALS-Dilithium. On the one hand, CRYSTALS-Kyber is a key-encapsulation mechanism (KEM) belonging to asymmetric cryptography. Whose security is based on the difficulty of solving the learning-with-errors (LWE) problem over module lattices. On the other hand, CRYSTALS-DIlithium is a Digital Signature Scheme (DSS). It is strongly secure under chosen message attacks based on the hardness of lattice problems over module lattices. The security notion means that an adversary with access to a signing oracle cannot produce a signature of a message whose signature he hasn't yet seen nor produce a different signature of a message he already saw signed. Then, both schemes (Kyber and Dilithium) are the candidate algorithms to be standardized by the NIST post-quantum cryptography project.

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Rosnet is a simulation library for Quantum circuits using Tensor Networks. It provides a mechanism to simulate large Quantum circuits in HPC machines.

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The advanced version of package 's2dverification'. It is intended for 'seasonal to decadal' (s2d) climate forecast verification, but it can also be used in other kinds of forecasts or general climate analysis. This package is specially designed for the comparison between the experimental and observational datasets. The functionality of the included functions covers from data retrieval, data post-processing, skill scores against observation, to visualization.

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SafeDE (Safe Diversity Enforcer) is hardware module provides light-lockstep support by means of a non-intrusive and flexible hardware module that preserves staggering across cores running redundant threads, thus bringing time diversity to avoid common cause failures.

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Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores (V1). SafeDM quantifies the diversity of each redundant processor to guarantee that CCF will not go unnoticed, and without needing to deploy lockstepped cores. SafeDM computes data and instruction diversity separately, using different techniques appropriate for each case.

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Safegantana enhances the baseline Sargantana core with safety properties employing a lockstep technology. Lockstep requires two instances of the Sargantana core and an extra logic that compares the inputs and outputs of these cores in order to identify error. With this technology, erroneous data can be detected before reaching the external system, and is a typical solution employed in safety critical systems domain, specially in automotive.

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SafeLS (Safe Lockstep): The Safe Lockstep (SafeLS for short) unit is a RISC-V open-source lockstep core based on Frontgrade Gaisler AB's NOEL-V core for the space domain, as well as its integration in the SELENE SoC that provides a complete microcontroller synthesizable on FPGA successfully assessed against space, automotive, and railway safety-critical applications in the past.

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The Safe Statistics Unit (SafeSU for short) is an RTL IP that implements several mechanisms for multicore timing interference verification, validation, and monitoring. It has been integrated into commercial space-graded RISC-V and SparcV8 MPSoCs.

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The Safe Traffic Injector (SafeTI for short) unit acts as an AHB or AXI4 Manager IP connected to the main AMBA bus. It functions as a core with limited capabilities, only generating transactions to the bus by reading and writing to memory address and controlled via APB registers. The injector works along with the multi-core setup instantiated on the platform and other peripherals and monitoring units. In order to generate traffic to the bus, the module must be first programmed with a series of descriptors describing the traffic pattern to be injected. Then, once the SafeTI module is configured and enabled, it performs a set of AMBA transactions based on the programmed data descriptors into a predefined memory address range.

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We note that many emerging AI-based functionalities are intrinsically stochastic (e.g., camera-based object detection), and hence, their correctness must be judged semantically, with room for variations across correct outcomes (e.g., confidence must be above a given threshold).
Building on this observation, we propose strategies to create DMR and TMR implementations of AI-based functionalities that bring not only fault tolerance against random hardware faults, but also against AI model inaccuracies. Those strategies, which can be realized with software-only means and ported to virtually any computing platform, build on input data modifications affecting the inference computations, but not the expected semantic output (e.g., introducing some limited random noise in the input data). Moreover, we have implemented a tool for image and video processing aimed at facilitating the reproducibility of our evaluation results, and enabling others to use it and conduct further research on input transformations.

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Software-only smart AI diverse redundancy. This solutions enables the execution of AI models redundantly and with diversity to mitigate the likelihood of a single fault, whether it is a random hardware fault or an AI model misprediction, to cause a failure. This solution is relevant for the use of AI software in the most safety-critical systems in, for instance, autonomous driving and unmanned vehicles. Ensures saafe AI integrtion in automotive, space and railway systems. It uniquely certifies solutions, addressing explainability,, supervision, traceability, and real-time compliance.

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Saiph is a Domain Specific Language developed at BSC for simulating physical phenomena modeled by Partial Differential Equations systems designed for users that are not experts in numerical methods neither programming for supercomputers

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Sargantana constitutes the third generation of Lagarto processors, the first open-source chips developed in Spain, within the framework of the DRAC project (Designing RISC-V-based Accelerators for next generation Computers) and is one of the most academically advanced open-source chips in Europe. The new Sargantana presents better performance than its two predecessors and is the first processor in the Lagarto family to break the gigahertz barrier in working frquency.

It is a 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI (RV64GV).

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SAURIA (Systolic Array tensor Unit for aRtificial Intelligence Acceleration) is a CNN (Convolutional Neural Network) accelerator that efficiently executes heavy computations needed for neural network algorithms, such as 2D convolutions and general matrix-matrix multiplications. The accelerator is meant to be loosely coupled to a host CPU, which must manage its local memories (fetch input data and extract results) and configure its execution through a memory-mapped interface. Once the host has prepared and started the execution, SAURIA will perform the convolution independently, and raise an interrupt upon full completion.

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Scanflow, developed by Lenovo and BSC, is a scalable library designed for managing end-to-end machine learning (ML) workflows. Its primary function is to streamline the deployment, supervision, and debugging of ML processes. Leveraging Docker containers, Scanflow ensures easy deployment, portability, and reproducibility of ML workflows, while also enabling scalability through integration with cluster orchestrators.

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Scord is an open-source data scheduling service that orchestrates asynchronous data transfers between different storage backends in an HPC cluster.

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Wind resource assesment and design for wind farm operators

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Tool set for exploration, visualization and query of ontologies.

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Software that analyzes gene expression data available in public databases such as GEO and ArrayExpress to study similarities between diseases by analyzing women and men separately. This software identifies first the sex of the samples based on the expression levels of genes on the Y chromosome, and then performs data normalization, differential expression, functional enrichment and study of similarities between diseases based on the differential expression profiles and the enriched biological processes. Software results are in turn made available for use by the scientific community.

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The Siesta code is a highly efficient and scalable software package used for performing electronic structure calculations and ab initio molecular dynamics simulations of molecules and solids. It is based on density functional theory (DFT) and employs low-scaling algorithms, which enable the study of very large systems at the atomic scale. BSC has significantly contributed to the efficient parallelization of Siesta, as well as the implementation of low-scaling solvers, enhancing its performance and usability on high-performance computing platforms.

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