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2005

Efficient Register File Management in High-ILP Processors

J. J. Alastruey, T. Monreal, V. Viñals, and M. Valero
Hierarchical Gaussian Topologies

M. Moreto, C. Martínez, R. Beivide, E. Vallejo, and M. Valero
Power and Performace Evaluation of Widened and Clustered VLIW Cores

M. Pericas, E. Ayguade, J. Zalamea, J. Llosa, and M. Valero
Performance Analysis of New Packet Trace Compression TCP Flow Clustering

R. Holanda, J. Verdú, J. García, and M. Valero
Effective Instruction Prefetching via Fetch Prestaging

IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium

A. Falcón, A. Ramirez, and M. Valero
Control-Flow Independence Reuse via Dynamic Vectorization

A. Pajuelo, A. González, and M. Valero
A Vector-uSIMD-VLIW Architecture for Multimedia Applications

E. Salami, and M. Valero
Workload Characterization and Stateful Networking Aplications

M. Valero, J. Verdú, M. Nemirovsky, and J. García
Architectural Impact of Statefull Networking APPlications

M. Valero, J. Verdú, M. Nemirovsky, and J. García
Hardware Support for Early Register Release

T. Monreal, V. Viñals, A. González, and M. Valero

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