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2004

Register-constrained Modulo Scheduling

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
Initial Evaluation of Multimedia Extensions on VLIW Architectures

E. Salami, and M. Valero
Performance and Power Evaluation of Clustered VLIW Processors with Functional Units

M. Pericas, E. Ayguade, J. Zalamea, J. Llosa, and M. Valero
Prophet/Critic Hybrid Branch Prediction

31st Annual International Symposium on Computer Architecture (ISCA-31)

A. Falcón, J. Stark, A. Ramirez, K. Lai, and M. Valero
Approaching a Smart Sharing of Resources in SMT Processors

Workshop on Complexity-Effective Design (WCED)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
A Complexity-Effective Decoding Architecture Based on Instruction Streams

Workshop on Complexity-Effective Design (WCED)

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
Implicit vs. Explicit Resource Allocation in SMT Processors

2004 Euromicro Symposium on Digital Systems Design (DSD 2004)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors

10th International Conference on High Performance Computer Architecture (HPCA-10)

A. Falcón, A. Ramirez, and M. Valero
Reducing Fetch Architecture Complexity Using Procedure Inlining

8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT)

O. J. Santana, A. Ramirez, and M. Valero
A latency conscious SMT branch predictor architecture

International Journal of High Performance Computing and Networking (IJHPCN)

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero

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