Marc Casas

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Biography

Marc Casas is a technical research lead at the Barcelona Supercomputing Center (BSC) and lecturer at the Universitat Politècnica de Catalunya (UPC). His research lays between computer architecture (e.g. memory address translation, vector architectures) and high-performance computing (e.g. sparse linear algebra, parallel deep learning). He is the technical lead of the SONAR (parallel SOftware and New ARchitectures) research group, composed of PhD students, engineers, and postdocs. Marc has lead BSC contributions to several european projects (Mont-Blanc2020, European Processor Initiative, etc.), and research collaborations with Intel and IBM. 

Marc has been at BSC since 2013. He was a postdoctoral research scholar at the Lawrence Livermore National Laboratory (LLNL) from 2010 to 2013. He received the Marie Curie and Ramón y Cajal Fellowships on 2014 and 2018, respectively. He obtained a 5-years degree in mathematics in 2004, and a PhD degree in Computer Science in 2010 from the Universitat Politècnica de Catalunya (UPC).

Selection of Recent Publications:

Parallel and High-Performance Computing:

  • Yuyao Niu, Marc Casas: BerryBees: Breadth First Search by Bit-Tensor-Cores. To appear at PPoPP 2025.
  • Alexandre de Limas Santana, Adrià Armejach, Marc Casas: Efficient Direct Convolution Using Long SIMD Instructions. PPoPP 2023. [PDF]
  • Constantino Gómez, Filippo Mantovani, Erich Focht, Marc Casas: Efficiently running SpMV on long vector architectures. PPoPP 2021. [PDF]
  • Luc Jaulmes, Miquel Moretó, Mateo Valero, Mattan Erez, Marc Casas: Runtime-guided ECC protection using online estimation of memory vulnerability. SC 2020. [PDF]

Computer Architecture:

  • Dimitrios Chasapis, Georgios Vavouliotis, Daniel A. Jiménez, Marc Casas: Instruction-Aware Cooperative TLB and Cache Replacement Policies. To appear at ASPLOS 2025.
  • Georgios Vavouliotis, Marti Torrents, Boris Grot, Kleovoulos Kalaitzidis, Leeor Peled, Marc Casas: To Cross, or Not to Cross Pages for Prefetching? To appear at HPCA 2025.
  • Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas: A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. HPCA 2024. [PDF]
  • Georgios Vavouliotis, Gino Chacon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jiménez, Marc Casas: Page Size Aware Cache Prefetching. MICRO 2022. [PDF]
  • Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jiménez, Marc Casas: Morrigan: A Composite Instruction TLB Prefetcher. MICRO 2021. [PDF]
  • Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Daniel A. Jiménez, Marc Casas: Exploiting Page Table Locality for Agile TLB Prefetching. ISCA 2021. [PDF]
 
 

Last edit: 21/05/2024