7.2 Journals

  • “Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86”. Future Generation Computer Systems 112, 832-847.
    JM Cebrian, A Barredo, H Caminal, M Moretó, M Casas, M Valero


    On the maturity of parallel applications for asymmetric multi-core processors.    J. Parallel Distributed Comput. 127: 105-115 (2019) Published on May 2019
    K.Chronaki,     M. Moretó, M. Casas, A. Rico, RM. Badia, E. Ayguadé, M. Valero

    Using Arm's scalable vector extension on stencil codes.The Journal of Supercomputing 76(3): 2039-2062 (2020)Published on 8th April 2019
    A. Armejach, H. Caminal, JM. Cebrian, R. Langarita, R. González-Alberquilla, C. Adeniyi-Jones, M. Valero, M. Casas, M. Moretó

    Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies.The Journal of Supercomputing 76(3): 1960-1979 (2020) Published on 4th April 2019.
    A. Barredo, JM. Cebrian, M. Valero, M. Casas, M. Moretó.

    A Hardware Runtime for Task-Based Programming Models.IEEE Trans. Parallel Distrib. Syst. 30(9): 1932-1946 (2019)Published on 26th March 2019.
    X. Tan, J. Bosch, C. Álvarez, D. Jiménez-González, E. Ayguadé, M. Valero

    Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications.Int. J. Parallel Program. 47(3): 343-344 (2019) Published on 23rd Marc 2019.
    F.Zhang, J. Zhai, M. Snir, H. Jin, H. Kasahara,     M. Valero.

    The international race towards Exascale in EuropeCCF Transactions on High Performance Computing Springer Singapore.
    F. Gagliardi, M. Moreto, M. Olivieri, M.Valero. 2019, pages 1-11.

    Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add IEEE Transactions on Very Large Scale Integration (VLSI) SystemI. Ratkovic , O. Palomar, M. Stanic, O. S.Ünsal, A. Cristal and M. Valero to be published

    La Inteligencia Artificial y los Nuevos Puestos de Trabajo Revista La Maleta.
    Numero 31, Septiembre-Octubre 2018, pp.49-53.

    Performance and energy effects on task-based parallelized applications. The Journal of Supercomputing

    H. Caminal, D. Caballero, J. M. Cebrián, R. Ferrer, M. Casas, M. Moretó, X. Martorell and M. Valero Vol 74, issue 6, pp 2627-2637, June 2018.

    Advances in the Hierarchical Emergent Behaviors (HEB) Approach to Autonomous Vehicles. IEEE Intelligent Transportation Systems Magazine.
    D. Roca, R. Milito, M. Nemirowsky and M. Valero. To be published

    Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. IEEE Trans. VLSI Syst. 26(4): 639-652 (2018)
    I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal and M. Valero

    Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. IEEE Transacton on Parallel and Distributed Processing.
    Vol. 26, Issue 5. Pp.1174-1187, May 2018. P. Caheny, Ll. Alvarez, S. Derradji, M. Valero, M. Moreto and M. Casas.

    A general guide to applying machine learning to computer architecture SUPERFRI. To be published in 2018.

    D. Nemirovsky, T. Arkose, N. Markovic, M. Nemirovsky, O. Unsal, A. Cristal and M. Valero.

    Asynchronous and Exact Forward Recovery for Detected Errors in Iterative SolversIEEE Computer Society – IEEE Transaction on Parallel and Distributed Systems. Volume: PP. Issue: 99.
    M. Moreto, L.Jaulmes, E. Ayguadé, J. Labarta, M. Valero and M. Casas. March 2018.

    Task Scheduling Techniques for Asymmetric Multi-core Systems. IEEE Transactions on Parallel and Distributed Systems; Volume 28, Issue 7, pp: 2074-2087, July 2017;
    K. Chronaki, A. Rico, M. Casas, M. Moretó, R. M. Badia, E. Ayguadé, J. Labarta and M. Valero.

  • An Integrated Vector-Scalar Design on an In-Order ARM Core ACM TACOTransactions on Architecture and Code Optimization Volume 14 Issue 2, May 2017
    M. Stanic, O. Palomar, T. Hayes, I. Ratkovic, A. Cristal, O. Unsakl and M. Valero
  • An Intengrated approach for tactical monitoring and data-driven spread forecasting of wildfiresFire Safety JournalM.M Valero, O. Rios, C. Mata, E. Pastor and E. Planas.
  • Hybrid/heterogeneous programming with ompss and its software/hardware implicationsProgramming Multicore and Many-core Computing Systems;Volume 86, pp: 101, February,2017
    E. Ayguade, R.M. Badia, P. Bellens, J. Bueno, I. Tsalouchidou Teruel and M. Valero.
  • Determinism at Standard-Library Level in TM-Based ApplicationsInternational journal of parallel programming; Volume 45, Issue 1, pp:17-29, February 2017
    V. Smiljković, O. Ünsal, A. Cristal and M. Valero.
  • The Hipeac Vision 2017 HIPEAC network of excellence. Pp:138; January, 2017
    M. Duranton, K. De Bosschere, C. Gamrat, J. Maebe, H. Munk and O. Zendra.
  • Emergent Behaviors in Internet of Things: The Ultimate Ultra-Large-Scale System IEEE-Micro Special Issue on IoT, Internet of Things; IEEE Micro November-Desember 2016; Issue 6; Volume 36
    D. Roca, D. Nemirosvky, M. Nemirosvjy, R. Milito and M. Valero 
  • Thread Assignment of Multicore/Multithreaded Processors: A Statistical Approach IEEE-TC. January 2016.Vol 65, Issue 1, pp.256-269 P. Radojkovic, P. Carpenter, M. Moretó, V. Cakarevic, J. Verdú, A. Pajuelo, F. J. Cazorla, M. Nemirovsky and M. Valero
  • PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite ACM Transactions on Architecture and Code Optimization (TACO), vol. 12, num. 4. Presented at International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Prague, Czech Republic, January 2016. D. Chasapis, M. Casas, M. Moretó, R. Vidal, E. Ayguadé, J. Labarta and M. Valero
  • New Benchmarking Methodology and Programming Model for Big Data Processing International Journal of Distributed Sensor Networks, vol. 2015, pp. 1-7, 2015 A. Kos, S. Tomažič, J. Salom, N. Trifunovic, M. Valero and V. Milutinovic
  • PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite ACM Transactions on Architecture and Code Optimization (TACO). Volume 12 Issue 4, December 2015 D. Chasapis, M. Casas, M. Moretó, R. Vidal, E. Ayguadé, J. Labarta and M. Valero
  • Sensible Energy Accounting with Abstract Metering for Multicore Systems ACM Transactions on Architecture and Code Optimization (TACO). Volume 12 Issue 4, December 2015 Q. Liu, M. Moretó, J. Abella, F. J. Cazorla, D. A. Jiménez and M. Valero
  • Picos: A Hardware Runtime Architecture Support for OmpSs Future Generation Computing Systems. Vol. 53, Dec. 2015, pp.130-139 F. Yazdanpanah, C. Álvarez, D. Jiménez-Colás, R. M. Badia and M. Valero
  • Kernel to user mode code transition aware hardware scheduler for Asymmetric Single-ISA Multi-Core processor IEEE Micro 35(4), July 2015 N. Markovic, D. Nemirovsky, O. Unsal, M. Valero and A. Cristal
  • On-the-fly adaptive routing for dragonfly interconnection networks Journal of Supercomputing. Vol.01/03/2015.71(3) pp. 1116-1142 M. García, E. Vallejo, J. R. Beivide, C. Camarero, M. Valero, G. Rodríguez and C. Minkerberg
  • Reimagining Heterogeneous Computing: a Functional Instruction Set Architecture (F-ISA) Computing Model IEEE Micro Special Issue on Alternative Computing Designs and Technologies 35(5), September 2015 D. Nemirovsky, N. Markovic, O. Unsal, M. Valero and A. Cristal
  • Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation TODAES-2013-P-723.R1.. ACM Transactions on Design Automation of Electronic Systems (TODAES). Vol.20 (1), pp. 10-25, November 1, 2014 B. Maric, J. Abella, F. J. Cazorla and M. Valero
  • TERAFLUX: Harnessing dataflow in next generation teradevices. Microprocessors and Microsystems - Embedded Hardware Design 38(8): 976-990 (2014) R. Giorgi, R. M. Badia, F. Bodin, A. Cohen, P. Evripidou, P. Faraboschi, B. Fechner, G. R. Gao, A. Garbade, R. Gayatri, S. Girbal, D. Goodman, B. Khan, S. Koliai, J. Landwehr, N. M. Lê, F. Li, M. Luján, A. Mendelson, L. Morin, N. Navarro, T. Patejko, A. Pop, P. Trancoso, T. Ungerer, I. Watson, S. Weis, S. Zuckermana and M. Valero
  • Runtime-Aware Architectures: A first Approach Journal on Supercomputing Frontiers and Innovations. First Issue. Vol. 1, n.1, pp 28-43 M. Valero, M. Moretó, M. Casas, E. Ayguadé and J. Labarta
  • Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators International Journal of Parallel Programming, vol. 42 (1), pp. 119-139, Feb 2014 S. Tomic, A. Cristal, O. Unsal, and M. Valero
  • Supercomputers: esencial for Sciences and Engineering Campus Milenio Journal. México D.F, Nov, 21, 2013 M. Valero
  • Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes IEEE Transactions on Very Large Scale Integration Systems. Vol. 22, (10). PP. 2212-2215, October, 1, 2014 B. Maric, J. Abella and M. Valero
  • Editorial. Revista Computación y Sistema Vol 18(4), 2014 M. Valero and U. Cortés
  • Per-task Energy Accounting in Computing Systems IEEE Computer Architecture Letters (CAL).Volume 13, num. 2, pp. 85-88, July 2014 Q. Liu, V. Jiménez, M. Moretó, J. Abella, F. J. Cazorla and M. Valero
  • Programmability and portability for exascale: Top down programming methodology and tools with StarSs In Journal of Computational Science, available online February, 11th. 2013 http://dx.doi.org/10.1016/j.jocs.2013.01.008, pp. 450-456V. Subotić, S. Brinkmann, V. Marjanović, R. M. Badia, J. Gracia, C. Niethammer, E. Ayguadé, J. Labarta and M. Valero
  • Moving from Petaflops to Petadata Communications of the ACM, Vol. 56, No. 5, pp. 39-42, May 2013 M. Flynn, O. Mencer, V. Milutinovic, G. Rakocevic, P. Stenström, R. Trobec and M. Valero
  • Overview of Acceleration Results of Maxeler FPGA Machines IPSI Transactions on Internet Research, July 2013, Volume 5, Number 1, pp. 1-4 J. Salom, H. Fujii and M. Valero
  • SMT Malleability in IBM Power5 and IBM Power6 Processors IEEE Transactions on Computers. Vol. 62, (4), pp. 813-826, April 2013 A. Morari, C. Boneti, R. Giogiosa, F. J. Cazorla, Chenyong, A. Buyuktosunoglu , P. Bose and M. Valero
  • Moving from petaflops (on simple benchmarks) to petadata per unit of time and power (on sophisticated benchmarks)” CACM, Communications of the ACM 56(5): 39-42, 2013G. Rakocevic, V. Milutinovic, O. Mencer, M. Flynn, R. Trobec, M. Valero and P. Stestrom
  • Programmability and Portability for Exascale: Top-Down Programming Methodology and Tools with StasSs Elsevier, In Journal of Computational Science, available online February, 11th. 2013 http://dx.doi.org/10.1016/j.jocs.2013.01.008, pp. 450-456V. Subotić, S. Brinkmann, V. Marjanović, R. M. Badia, J. Gracia, C. Niethammer, E. Ayguadé, J. Labarta and M. Valero
  • Fair CPU Accounting in CMP+SMT Processors TACO. Vol. 9, (4), January 2013, pp.50 C. Luque, M. Moreto, F. J. Cazorla, and M. Valero
  • Hardware Support for accurate per-task energy metering in multicore systems TACO, 10 (4), 50, 2013 Q. Liu, M. Moretó, V. Jiménez, J. Abella, F. J Cazorla and M. Valero
  • Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors IEEEE TPDS, Transactions on Parallel and Distributed Systems”.Vol. 24, no. 12, pp. 2513-2525, 2013 P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. J. Cazorla, M. Nemirovsky and M. Valero
  • The Problem of Evaluating CPU+GPU Systems with 3D Visualization Appliacations IEEE Micro Jounal. Issue Nov/Dec, Vol. 32, Issue 6, pp. 17-27, year 2012 J. Verdú, A. Pajuelo and M. Valero
  • Resource-bounded multicore emulation using Beefarm Microprocessors and Microsystems - Embedded Hardware Design. Vol. 36, No. 8, pp. 620-631, Nov. 2012 O. Arcas, N. Sönmez, G. Sayilar, S. Singh, O. S. Unsal, A. Cristal, I. Hur and M. Valero
  • Circuit Design of a Dual-Versioning L1 Data Cache Integration the VLSI Journal, Lausanne, Switzerland, May 2011, pp: 325-330Azam Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur and Mateo Valero
  • SMT Malleability in IBM Power5 and IBM Power6 Processors IEEE Transactions on Computer Architecture. Volume: PP , Issue: 99 • January 24, 2012 A. Morari, C. Boneti, R. Giogiosa, F. J. Cazorla, Chenyong, A. Buyuktosunoglu , P. Bose and M. Valero
  • Understanding the Future of Energy-Performance Trade-off Via DVFS in HPC Environment IEEE Journal of Parallel and Distributed Computing, IEEE-JPDC. Vol. 72, pp.579-590. January, 2012 M. Etinski, J. Corbalán, J. Labarta and M. Valero
  • CPU Accounting for Multicore Processors IEEE Transactions on Computers. Vol. 61, Number 2, pp. 251-264, 2012 C. Luque, M. Moretó, F. J. Cazorla, R. Gioiosa, A. Buyukttosunoglu and M. Valero
  • Energy-Aware Accounting and Billing in Large-Scale Computing Facilities IEEE Micro Jornal. Vol 31 (3), pp. 60-71, 2011 V. Jiménez, F. J. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, P. Bose and M. Valero
  • Simulating Whole Supercomuter Applications IEEE Micro Jornal. Vol 31 (3), pp. 32-45, 2011 J. González, M. Casas, M. Moretó, J. Giménez, A. Ramírez, J. Labarta and M. Valero
  • Assessing Accelerator-based HPC Reverse Time Migration – IEEE TPDS, IEEE Transaction on Parallel and Distributed Systems. Vol. 22, No 1, pp. 147-162, January 2011 M. Araya-Polo, J. Cabezas, M. Hanzich, M. Pericàs, F. Rubio, I. Gelado, M. Shafiq, E. Morancho, N. Navarro, E. Ayguadé, J. M. Cela and M. Valero
  • The International Exascale Software Project Roadmap IJHPCA, INternnational Journal of High Performance Computer Applications, Vol 25 (1), pp: 3-60, 2011 J. Dongarra et al
  • Hybrid Transactional Memory with Pessimistic Concurrency Control International Journal of Parallel Programming, Vol. 39 (3), pp. 375-396, 2011 E. Vallejo, S. Sanyal, T. Harris, F. Vallejo, R. Beivide, O. Unsal, A. Cristal and M. Valero
  • Dynamic Cache Partitioning Based on the MLP of Cache Misses Thansactions on High-Performance Embedded Architectures and Compilers III. Lectures Notes on Computer Science, Vol. 6590, pp. 3-23, 2011 M. Moretó, F. J. Cazorla and M. Valero
  • Profiling and Optimizing Transactional Memory Applications International Journal of Parallel Programming (IJPP) S. Stipic, F. Zyulkyarov, T. Harris, O. Unsal, A. Cristal, I. Hur and M. Valero
  • Characterization of Power and Termal Behavior of Power6 System Invited paper. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Vol. 1, number 3, September 2011, pp. 228-241 V. Jiménez, F. J. Cazorla, R. Gioiosa, M. Valero, C. Boneti, E. Kursun, C. Y Cher, C. Isci, A. Buyuktosunoglu and P. Bose
  • Fuzzy region Computation IEEE Transactions on Computers. To be published… C. Álvarez, J. Corbal and M. Valero
  • Refundar a las Universidades  Campus Milenio Journal. México. February, 2011, pp. 8-9
  • Co-editors of the special Issue: Multicore, the View from Europe IEEE Micro Journal. September- October 2010, pp. 2-4 M. Valero and N. Navarro
  • Utilization Mriven Power-Aware Parallel Job Scheduling Computer Science – Research and Development, Springer Verlag, Vol. 25, Numbers 1-2, May 2010, pp. 207-216 M. Etinski, J. Corbalán, J. Labarta and M. Valero
  • Assessing Accelerator-based HPC Reverse Time Migration– IEEE TPDS, IEEE Transaction on Parallel and Distributed Systems. Vol. 22, No 1, pp. 147-162, January 2011 M. Araya-Polo, J. Cabezas, M. Hanzich, M. Pericàs, F. Rubio, I. Gelado, M. Shafiq, E. Morancho, N. Navarro, E. Ayguadé, J. M. Cela and M. Valero
  • On the Problem of Evaluating the Performance of Multiprogrammed Workloads IEEE Transaction on Computers; Volume 59, Issue 10, pp: 1722-1728, December 2010F. J. Cazorla, A. Pajuelo, O. J. Santana and M. Valero
  • ITCA: Inter-Thread Conflict-Aware CPU Accounting for CMPs IEEE Computer Architecture Newsletter, Volume 8, Issue 1, pp: 17-20; January 2009R. Luque, M. Moretó, A. Buyukstosumoglu, F. J. Cazorla, R. Giogiosa, P. Bose and M. Valero
  • Hybrid Transactional Memory with Pessimistic Concurrency Control International Journal of Parallel Programming, Volume 39, Issue 3, pp: 375-396, 2011.E. Vallejo, S. Sanyal, T. Harris, F. Vallejo, R. Beivide, O. Unsal, A. Cristal and M. Valero
  • "Investigar… per a qué?" Informations of the "Universidad Politécnica de Cataluña" Journal. Number 226, January 2010, pp.2 M. Valero
  • The International Exascale Software Project: A Call to Cooperative Action by the Global High-Performance Community The International Journal of High Performance Computing Applications. Vol. 23, No. 4, pp. 309-322, Winter 2009 J. Dongarra, P. Beckman, P. Aerts, F. Capello, T. Lippert, S. Matsuoka, P. Messina, T. Moore, R. Stevens, A. Trefethen and M. Valero
  • BSC Vision Towards Exascale The International Journal of High Performance Computing Applications. Vol. 23, No. 4, pp. 340-343, Winter 2009 J. Labarta, E. Ayguadé and M. Valero
  • Turbocharging Boosted Transactions or: How I Learnt to Stop Worrying and Love Longer Transactions ACM Sigplan Notices 2009;Vol. 44:307-308 C. Kulkarni, O. Unsal, A. Cristal, E. Ayguadé and M. Valero
  • FlexDCP: a QoS framework for CMP architectures ACM OSR, Operating Systems review Journal.Special issue on The Interaction Among the OS, the Compiler, and Multicore Processors.FlexDCP: a QoS framework for CMP architectures
    To appear
    Available Task-level Paralellism on the CellBE Scientific Programming Jornal. Special Issue on Cell Processor, Volume 43, Issue 2, pp: 86-96, April 2009.
    A. Rico, A. Ramírez and M. Valero
  • Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture Avances en Sistemas e Informática. Colombia. Vol. 6, No. 1, June 2009. ISSN 1657-7663 M. Álvarez, A. Ramírez, M. Valero, A. Azevedo, C. Meenderinck and B. Juurlink
  • DIA: A Complexity Effective Decoding Architecture IEEE Transaction on Computers, Vol 58, No4, April 2009, pp 10448-10462 O. J. Santana, A. Ramírez, A. Falcón and M. Valero
  • Transactional Memory and OpenMP International Journal of Parallel Programming - Sep 2008 M. Milovanovic, R. Ferrrer, O. Unsal, A. Cristal, X. Martorell, E. Ayguadé, J. Labarta and M. Valero
  • A Framework for Managing Multicore Resources IEEE Micro. Special Issue on Interaction of Computer Architecture and Operating Systems in the Multicore Era. May-June 2008, Vol. 28, Issue 3, pp. 6-16 K. J. Nesbit, M. Moretó, F. J. Cazorla, A. Ramírez, M. Valero and J. E. Smith
  • Nebelung: Execution Environment for Transactional OpenMP International Journal of Parallel Programming. Vol 36, number 3 - May 2008 M. Milovanovic, R. Ferrer, V. Gajinov, O. Unsal, A. Cristal, E. Ayguadé and M. Valero
  • Soft Real-Time Scheduling on SMT Processors with Explicit resource Allocation ARSC 2008, International Conference on Architecture and Computing Systems. Dresden, Germany, Feb. 25-28, 2008. LNCS-4934.ISBN 978-3-540-78152-3. February 2008, pp173-187 C. Boneti, F. J. Cazorla, R. Giogiosa and M. Valero
  • Supercomputing for the Future, Supercomputer for the PastKeynote Lecture. HiPEAC 2008 Conference. High Performance Embedded Architecture Embedded Architectures and Compilers. LNCS 4917, pp. 3-5. Göteborg, Sweden, January 2008 M. Valero and J. Labarta
  • Power-efficient VLIW design using clustering and widening IJES, International Journal on Embedded Systems, Volume 3, Issue 3, pp: 141-149, 2008.M. Pericàs, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Decoupled State-Execute Architecture LNCS 4759, pp. 68-78. Paper from ISHPC-2005. International Symposium on High Performance Computers. Nara, Japan. September 7-9, 2005. January 2008 M. Pericàs, A. Cristal, R. González and M. Valero
  • Increasing the Performance of Haskell Software Transactional Memory Trends in Functional Programming, Volume 8, Intellect, 2008 (to appear). ISBN 9781841501963 N. Sonmez, C. Perfumo, S. Stipic, A. Cristal, O. Unsal and M. Valero
  • Exploiting Instruction Locality with a Decoupled kilo-Instruction Processor LNCS, pp. 56ñ67. Paper from ISHPC-2005. International Symposium on High Performance Computers. Nara, Japan. September 7-9, 2005. January 2008 M. Pericàs, A. Cristal, R. González, D. A. Jiménez and M. Valero
  • Workload Characterization and Stateful Networking Applications LNCS 4759, pp.130-141. Paper from ISHPC-2005. International Symposium on High Performance Computers. Nara, Japan. September 7-9, 2005. January 2008 J. Verdú, M. Nemirovsky, J. García and M. Valero
  • Multiple Stream Prediction Best paper Award. LNCS 4759, pp. 1-16. Paper from ISHPC-2005. International Symposium on High Performance Computers. Nara, Japan. September 7-9, 2005. January 2008 O. J. Santana, A. Ramírez and M. Valero
  • Enlarging Instruction Streams in IEEE Transactions on Computers. Vol 56, No 10, pp. 1342-1357, October, 2007 O. J. Santana, A. Ramírez and M. Valero
  • Transactional Memory: An Overview  in IEEE-Micro Journal,  Volume 27, Issue 3, pp: 8-29, 2007 T. Harris, A. Cristal, O. Unsal, E. Ayguadé, F. Gagliardi, B. Smith and M. Valero
  • Expalining Dyanamic Cache Partitioning Speed Ups IEEE Computer Architecture Letters. Vol. 16, No.1, March 2007 M. Moretó, F. J. Cazorla, A. Ramírez and M. Valero
  • Predictable Performance in SMT processors: Synergy Between the OS and SMTs IEEE Transactions on Computers. Volume 55, Number 7. July, 2006, pp. 785-799 F. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramírez and M. Valero
  • A DRAM/SRAM Memory Scheme for Fast Packet Buffers IEEE Transactions on Computers. Vol. 55 No. 5, pp. 588-602, May 2006 J. Vidal, M. March, Ll. Cerdá, J. Corbal and M. Valero
  • Speculative Execution for Hiding Memory Latency Computer Architecture News, Vol. 33, No. 3, June 2005. Special Issue: MEDEA 2004 Workshop, pp. 49-56 A. Pajuelo, A. González and M. Valero
  • Te Impact of Traffic Aggregation on the Memory Performance of Networking Applications Computer Architecture News, Vol. 33, No. 3, June 2005. Special Issue: MEDEA 2004 Workshop, pp.57-62 X. Verdú, M. Nemirosvky, J. García and M. Valero
  • Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors IEEE CAL, Computer Architecture Letters, July, 2005 T. Morad, U. Weiser, A. Kolodny, M. Valero and E. Ayguadé
  • Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications ACM Transactions on Architecture and Code Optimization, TACO Journal. Vol 2, Issue 2, pp. 199-219, June 2005 E. Salami and M. Valero
  • Kilo-instruction Processors: Overcoming the Memory Wall IEEE-Micro Journal. Special Issue May/Jun05 Future trends of microprocessors A. Cristal, O. J. Santana, F. J Cazorla, M. Galluzzi, T. Ramírez and M. Valero
  • An Optimized Front-End Physical Register File with Banking and Writeback Filtering Lectures Notes on Computer Science, 3471 on “Power Aware Computer Systems”, pp. 1-14, 2005 M. Pericás, R. González, A. Cristal, A. Veidenbaum and M. Valero
  • Fuzzy Memoization for Floating Point Multimedia Applications IEEE Transactions on Computers. Vol. 54, No 7, July 2005, pp 922-927 C. Álvarez, J. Corbal and M. Valero
  • Software Trace Cache IEEE Transactions on Computers, Volume 54, Number 1, January 2005, pp.22-35 A. Ramírez, J. L. Larriba- Pey and M. Valero
  • Prophet/Critic Hybrid Branch Prediction IEEE Micro Journal. January-February, 2005 A. Falcón, J. Stack, A. Ramírez, K. Lai and M. Valero
  • Hardware Support for Early Register Release IJHPCN. International Journal on High Performance and Networking. Vol. 3, No 2/3, pp. 83-94, 2005 T. Monreal, V. Viñals, A. González and M. Valero
  • Towards Kilo-instruction Processors ACM Transactions on Architecture and Code Optimization, TACO Journal. Vol. I, Issue 4, December 2004 A. Cristal, O. J. Santana, J. Martínez and M. Valero
  • Initial Evaluation of Multimedia Extensions on VLIW Architectures Lectures Notes on Computer Science. Editor Springer-Verlag, Volume 3133, November 2004 E. Salami and M. Valero
  • Register-constrained Modulo Scheduling IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 6, June 2004 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • A ow-Complexity Fetch Architecture for High-Performance Superscalar Processors ACM Transactions on Architecture and Code Optimization, TACO Journal. vol 1, no. 2, pp 220-245, June 2004 O. J. Santana, A. Ramirez, J. L. Larriba-Pey, and M. Valero
  • DCache Warn: An I-Fetch Policy to Increase SMT Efficiency International Journal of Parallel and Distributed Computing, IJPDC. Elsevier Science. ISBN: 0-7695-2132-0, June 2004F. J. Cazorla, E. Fernández, A. Ramírez and M. Valero
  • Performance and Power Evaluation of Clustered VLIW Processors with Functional Units IJES: International Journal on Embedded Systems. Volume 3133, November 2004 M. Pericàs, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Software and Hardware Techniques to Optimize Register File Utilization in VLIW International Journal of Parallel Programming, accepted for publication, Volume 32, Issue 6, pp:447-474, December 2004J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • Power and Performace Evaluation of Widened and Clustered VLIW Cores LNCSxxxx, 2005 (to be published) M. Pericàs, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Late Allocation and Early Release of Physical Registers IEEE Transactions on Computers. Vol 53, No 10, pp. 1244-1259. October 2004 T. Monreal, V. Viñals, J, González, A. González, M. Valero
  • QoS for High Performance SMT Processors for Embedded Systems IEEE-Micro Journal, July-August 2004 F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramírez and M. Valero
  • Future ILP Processors IJHPCN. International Journal of High Performance Computing and Networking.  Volume 2, Issue 1, pp: 1-11, 2004A. Cristal, D. Ortega, J. Llosa and M. Valero
  • Dynamic Memory Instruction Bypassing IJPP, International Joiurnal on Parallel Processing. Special issue on selected papers from ICS-2003 (Internatinal Conference on Supercomputing), Volume 32, Issue 3, pp: 199-224, May 2004D. Ortega, M. Valero and E. Ayguadé
  • A Partitioned Instruction Queue to Reduce Instruction Wakeup Energy IJHPCN. International Journal of High Performance Computing and Networking. Volume I, Issue 4, pp 153-161, January 2004A. Ramírez, A. Cristal, A. Veidenbaum, L. Villa and M. Valero
  • High Performance and Low Power VLIW for Numerical Applications IJHPCN. International Journal of High Performance Computing and Networking. Volume 1, Issue 4, January 2004M. Pericàs, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • A Latency-Conscious SMT Branch Prediction Architecture ISHPC-V. IJHPCN. International Journal of High Performance Computing and Networking. Volume 2, Issue 1, pp: 11-21, 2004A. Falcón, O. J. Santana, A. Ramírez and M. Valero
  • Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors IJHPCN. International Journal of High Performance Computing and Networking. Volume 2, Issue 1, pp: 45-54, 2004F. J. Cazorla, E. Fernández, A. Ramírez and M. Valero
  • A Case for Resource Conscious Out-of-Order Processor: Towards Kilo-instructions in-flight Processors ACM Computer Architecture News. Special Issue: MEDEA Workshop.  March 2004 A. Cristal, J. Martínez. J. Llosa and M. Valero
  • A Case for Resource-conscious Out-of-order Processors IEEE TCCA Computer Architecture Letters. Volume 2, Oct. 2003 A. Cristal, J. F. Martinez, J. Llosa and M. Valero
  • Register Constrained Modulo Scheduling at IEEE TPDS, Transactions on Parallel and Distributed Systems; Volume 15, Issue 6, June 2004 J. Llosa, J. Zalamea, E. Ayguadé and M. Valero
  • Software Trace Cache at IEEE Transactions on Computer Architecture. Volume 54, Issue 1, pp: 22-35,ISSN: 0018-9340, January 2005 A. Ramírez, O. Santana, J-L. Larriba-Pey and M. Valero
  • Kilo-Instruction Processors Invited Paper. ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp-10-25. October, 2003 A. Cristal, D. Ortega, J. Llosa and M. Valero
  • A Simple Low-Energy Instruction Wakeup Mechanism ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp-99-112. October, 2003 A. Ramírez, A. Cristal, A. V. Veidenbaum, L. Villa and M. Valero
  • Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp. 113-126. October, 2003 M. Pericàs, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Tolerating Branch Predictor Latency on SMT Processors ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp.86-98. October, 2003 A. Falcon, O. J. Santana, A. Ramírez and M. Valero
  • Improving Memory Latency Aware Fetch Policies for SMT Processors ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp-70-85. October, 2003 F. J. Cazorla, E. Fernández, A. Ramírez and M. Valero
  • A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications TOCS: Theory of Computing Systems, Vol. 36, pp. 575-593 Sept. 2003. Springer Verlag, New York. ISSN 1432-4350 F. Quintana, J. Corbal, R. Espasa and M. Valero
  • MIRS: Modulo Scheduling with Integrated Register Spilling Languages and Compilers for Parallel Computing. Lecture Notes in Computer Science LNCS 2624, pp. 239-253, May 2003 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • Costo Energético de la Revolución Informática Revista de Libros. Number 65. May 2002, pp.30-31. ISSN: 1137-2249 M. Valero
  • Errata on “Measuring Experimental Error in Microprocessor Simulation ACM Computer Architecture News, Vol. 30, No.1, March 2002, pp.2-4 R. Desikan, D. Bourger, S. W. Keckler, Ll. Cruz, F. Latorre, A. González and M. Valero
  • Software Trace Cache for Commercial Applications IJPP, the International Journal on Parallel Programming. Volume 30, Issue 5, pp: 373-395, October 2002A. Ramírez, J.L. Larriba-Pey, C. Navarro, M. Valero and J. Torrellas
  • Initial Results on Fuzzy Floating Point Computation for Multimedia Processors IEEE TCCA Letters. January 2002 C. Alvarez, J. Corbal, E. Salami and M. Valero
  • Parallel Architecture and Compilation Techniques: Selection of Workshop Papers, Guests Editors Introduction ACM Computer Architecture News. Vol. 29, No. 5, December 2001, pp 9-12 S. Bartolini, R. Giorgi, J. Protic, C. A. Prete and M. Valero
  • Investigation National Awards Industry and Mining Journal. Number 346, Dec. 2001, pp. 29-32. Published by the "Consejo Superior de Colegios de Ingenieros de Minas". ISSN: 1137-8042 M. Valero
  • Instruction Fetch Invited Paper. IEEE Proceedings of the IEEE. Special Issue on Microprocessor Architectures and Compiler Technology, Vol 89, Issue 11,Nov. 2001, pp.1588-1609 A. Ramírez, J-L. Larriba- Pey and M. Valero
  • Cost-concious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures IEEE Transactions on Computers. Vol. 50, Issue 10. October 2001, pp. 1033-1051 D. López, J. Llosa, M. Valero and E. Ayguadé
  • Early 21 st. Century Processors IEEE Computer Magazine. Special Issue. Guest Editorial, April 2001. pp 47-51 S. Vajapeyam and M. Valero
  • Lifetime-sensitive Modulo Scheduling in a Production Environment IEEE Transactions on Computers. Vol. 50, Number 3. March 2001, pp. 234-249 J. Llosa, E. Ayguadé, A. González, M. Valero and J. Eckart
  • of the International Conference on High-Performance Computing, HiPC-7 Editor. Lectures Notes on Computer Science number 1970. Bangalore, Dec. 2000. ISBN 3-540-41429-0 M. Valero, V. Prasanna and S. Vajapeyam
  • High Performance Computing. Third International Symposium, ISHPC 2000 Editor. Lectures Notes on Computer Science number 1940. Tokyo, October 2000. ISBN 3-540-41128-3 M. Valero, K. Joe, M. Kitsuregawa and H. Tanaka
  • A Stream Processor Front-end IEEE Computer Society Technical Committee on Computer Architecture Newsletter. June 2000, pp 10-13 A. Ramírez, J. L. Larriba-Pey and M. Valero
  • Dynamic Register Renaming Through Virtual-Physical Registers The Journal of Instruction Level Parallelism, vol.2, May 2000. (http://www.jilp.org/vol2) T. Monreal, A. González, M. Valero, J. González and V. Viñals
  • "Computadors per al proper mil.leni"  TERAFLOP Journal, number 45. Oct. 1999, pp. 6-8 M. Valero
  • The Evolution of Cache Memories Special Issue on Cache Memory IEEE, Transactions on Computers. pp. 97-99. February 1999 M. Valero and V. Milutinovic
  • Registers Size Influence on Vector Architectures Lectures Notes on Computer Science, Springer Verlag. Vol. 1573, 1999. pp. 439-451 L. Villa, R. Espasa and M. Valero
  • A Comparison between Superscalar and Vector Processors Lectures Notes in Computer Science, Springer-Verlag. Vol. 1573, 1999. pp. 548-560 F. Quintana, R. Espasa and M. Valero
  • A Simulation Study of Decoupled Vector Architectures Journal of Supercomputing, Kluwer Academic. Vol. 14, number 2, Sep/October 1999, pp. 129-152 R. Espasa and M. Valero
  • Modulo Scheduling with Reduced Register Pressure IEEE Transactions on Computers. Vol. 47, No. 6. June 1998, pp. 625-638 J. Llosa, M. Valero, E. Ayguadé and A. González
  • Quantitative Evaluation of Register Pressure on Software Pipeline Loops International Journal of Parallel Programming. Plenum Publishing Corporation. Vol. 26, No 2. February 1998 pp. 121-142 J. Llosa, E. Ayguadé and M. Valero
  • Exploiting Instruction and Data-Level Parallelism IEEE Micro Journal. Vol. 17, No 5, Sep/October 1997, pp. 20-27 R. Espasa and M. Valero
  • Software Management of Selective and Dual Data Caches IEEE Computer Society. Technical Committee on Computer Architecture. March 1997, pp 3-10 F. J. Sánchez, A. González and M. Valero
  • Arquitectura de los Procesadores Electronic World. Editorial Marcombo. November 1996, pp. 78-84 M. Valero y A. González
  • Supercomputadores Science, Technology and Environment Annuary. El Pais, 1996, pp. 342-347. ISBN 84-86459-64-8 M. Valero
  • Centro de Computación y Comunicaciones de Cataluña Physics Journal. Editor: Physics Catalan Society. 1st semester 1996, pp. 40-45 M. Valero
  • Analyzing Reference Patterns in Automatic Data Distribution Tools International Journal of Parallel Programming. Plenum Publishing Corporation. Vol. 23, No 6, December 1995, pp. 515-535 E. Ayguadé, J. Labarta, J. García, M. Gironès and M. Valero
  • Vector Multiprocessors with Arbitrated Memory Access ACM, Computer Architecture News. Vol. 23, No 2, May 1995, pp 243-252 M. Peirón, M. Valero, E. Ayguadé and T. Lang
  • Increasing the Number of Conflict-Free Vector Access IEEE Transactions on Computers. Vol. 44, No 5, May 1995, pp 634-646 M. Valero, T. Lang, M. Peirón and E. Ayguadé
  • Network Synchronization and out-of-order Access to Vectors Parallel Processing Letters. December 1994. pp. 405-417. No 4, Vol 4 M. Valero, E. Ayguadé and M. Peirón
  • Synchronized Access to Streams in Multiprocessors IEEE TC on Computer Architecture Newsletter, 1993, pp. 37-41 M. Peiron, M. Valero, E. Ayguadé and T. Lang
  • "Arquitectura de los Computadores para Simulación" COTEC  documents about the technological challenges. Number 3: “Simulación”. Dec. 1993, pp. 32-39 M. Valer and, E. Ayguadé
  • Automatic Data-Mapping for Distributed-Memory Multiprocessor Systems International Journal of Mini and Microcomputers. Vol 15, No. 3. 1993, pp. 109-115 J. Torres, E. Ayguadé, J. Labarta, J. M. Llabería and M. Valero
  • Multilevel Orthogonal Blocking for Dense Linear Algebra Computations IEEE TC on Computer Architecture Newsletter. 1993, pp. 10-14 J. J. Navarro, A. Juan, M. Valero, J. M. Llabería and T. Lang
  • Conflict-Free Access to Streams in Multiprocessor Systems Microprocessing and Microprogramming Vol. 38, numbers 1-5, p. 119-130. Sept. 1993 M. Peirón, M. Valero, E. Ayguadé and T. Lang
  • A Method for Implementation of One-Dimensional Systolic Algorithms with Data Contraflows Using Pipelined Functional Units Journal of VLSI Signal Processing. Vol. 4, 1992. Editorial Kluwer Academic Publishers, pp. 7-25 M. V. García, J. J. Navarro, J. M. Llabería, M. Valero and T. Lang
  • Increasing the Number of Strides for Conflict-Free Vector Access ACM Computer Architectures News, May 1992, Vol. 20, pp. 372-381 M. Valero, T. Lang, J. M. Llabería, M. Peirón, E. Ayguadé and J. J. Navarro
  • Conflict-Free Strides for Vectors in Matched Memories Parallel Processing Letters. Edit. World Scientific. Vol. 1. No. 2, December 1991, pp. 95-102 M. Valero, T. Lang, J. M. Llabería, M. Peirón, J. J. Navarro and E. Ayguadé
  • A Block Algorithm and Optimal Fixed-Size Systolic Array Processor for the Algebraic Path Problem Journal of VLSI Signal Processing 1, pp. 153-162. Dec. 1989. Kluwer Academic Publishers, Boston F. Núñez and M. Valero
  • LU Decomposition on a Linear Systolic Array Processor International Journal of Mini and Microcomputers. Vol. 11, No. 1, pp. 4-8, 1989 J. J. Navarro, J. M. Llabería, F. Núñez and M. Valero
  • Proyectos Europeos: Algunas experiencias e ideas relacionadas con ESPRIT Revista Mundo Electrónico. Editorial Marcombo. No. 200. Nov. 1989, pp. 375-379 M. Valero
  • Systematic Adaptation of Systolic Algorithms to the Hardware ACM Computer Architectures News, 1989, pp. 96-104 M. V. García, J. J. Navarro, J. M. Llabería and M. Valero
  • Arquitecturas RISC Journal “Ingeniería: Cálculo, diseño y fabricación”. Hewlett Packard, Vol. 3, Sept. 1988 M. Valero
  • Partitioning: An Essential Issue to Map Algorithms Into Systolic Array Processors Special issue of IEEE Computer Magazine on the Subject: “Systolic Arrays: From Concept to Implementation”. July 1987, Vol. 20, No. 7, pp. 77-89 J. J. Navarro, J. M. Llabería and M. Valero
  • A Discrete Optimization Problem in Local Area Networks and Data Aligment IEEE Transactions on Computers. June 1987, Vol. C-36, pp.702-713 M. A. Fiol, J. L. Yebra, I. Alegre and M. Valero
  • Supercomputadores Electronic World Journal. Editorial Marcombo. Dec. 1986, pp. 117-129 M. Valero, J. M. Llabería, J.R. Beivide
  • Computing Size-Independent Matrix Problems on Systolic Array Processors ACM, Comp.Architecture News. Vol. 14, Junio 1986, pp. 271-278 J. J. Navarro, J. M. Llabería and M. Valero
  • Exact an Approximate Models for Multiprocessor Systems with Single Bus and Distributed Memory International Journal of Mini and Microcomputers, Vol. 8, No. 2, pp. 44-48, 1986 E. Sanvicente, M. Valero, T. Lang and I. Alegre
  • Optimization of Double-Loop Structures for Local Networks Int. Journal of Mini and Microcomputers, Vol. 8, No. 2, pp. 40-44, 1986 M. A. Fiol, M. Valero, T. Lang and I. Alegre
  • Analysis and Simulation of Multiplexed Single Bus Networks with and without Buffering ACM, Computer Architecture News. Vol. 13, 1985, pp. 414-421 J. M. Llabería, M. Valero, J. Labarta and E. Herrada
  • Reduced Interconnection Networks Based in the Multiple-Bus for Multiprocessor Systems International Journal of Mini and Microcomputers, Vol. 6, Núm. 1, pp. 4-9, 1984 M.A.Fiol, M. Valero, J.L. Andrés and T. Lang
  • "Redes de Interconexión para Sistemas Multiprocesadores" Electronic World Journal. Ed. Marcombo. Sept. 1983, pp. 117-129 M. Valero, E. Sanvicente, J. M. Llabería, J. Labarta
  • A Performance Evaluation of the Multiple-Bus Network for Multiprocessor Systems ACM SIGMETRICS Performance Evaluation Review. Special issue. August 1983, pp. 200-206 M. Valero, E. Sanvicente, J. M. Llabería, T. Lang and J. Labarta
  • Reduction of Connections for Multibus Organization IEEE, Transaction on Computers, Vol. C-32, No. 8, August 1983 1983 T. Lang, M. Valero and M. A. Fiol
  • "Optimización de redes locales en doble anillo" Electronic World Journal. Editorial Marcombo. March 1983, pp. 91-99 M.A. Fiol, J. L. Andrés Yebra, I. Alegre and M. Valero
  • Bandwidth of Crossbar and Multibus Connections for Multiprocessors IEEE, Transactions on Computers. Vol. C-31, No. 12, Dic. 1982, pp. 1227-1234 T. Lang, M. Valero and I. Alegre
  • M-users, B-Servers Arbiter for Multibus Multiprocessor Microprocessing and Microprogramming. The Euromicro Journal. August 1982, pp. 1-18 T. Lang and M. Valero
  • "Sistemas de Ficheros de Discos Flexibles para Microcomputadores" Electronic World Journal. Ed. Marcombo.pp. 95-103. Nov. 1981 A. Alcalá, M. Valero, C. Rosell and J. Alastruey
  • "Arquitectura de los Microprocesadores de 16 bits: Estudio de la familia NS-16000" (2a. parte)”. Electronic World Journal. Ed. Marcombo, pp. 120-130, Nov. 1981 M. Valero and D. Vidal
  • "Arquitectura de los Microprocesadores de 16 bits: I-8086, Z-8000 y M- 68000" Electronic World Journal. Editorial Marcombo, pp. 101-117. December 1980 M. Valero
  • "Sistemas Multiprocesador: Características y Posibilidades" NOVATICA Journal, pp. 46-58, Nov-Dec. 1979 M. Valero, M. Medina and E. Herrada
  • Sección Micromundo en la revista Mundo Electrónico Editorial Marcombo, during the months of Mayo to September 1978 A. Alabau and M. Valero