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2001

Strategies for Efficient Exploitation of Loop-Level Parallelism in Java Concurrency and Computation

Concurrency and Computation: Practice and Experience

J. Oliver, J. Guitart, E. Ayguade, N. Navarro, and J. Torres

2000

A Stream Processor Front-end

IEEE Technical Committee on Computer Architecture Newsletter

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
The Effect of Code Reordering on Branch Prediction

International Conference on Parallel Architectures and Compilation Techniques (PACT 2000)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
On the Performance of Fetch Engines Running DSS Workloads

6th International Euro-Par Conference (EuroPar'2000)

C. Navarro, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Fetch Engines and Databases

3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3)

C. Navarro, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Semi-static Branch Prediction for Optimized Code Layouts

3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Trace Cache Redundancy: Red & Blue Traces

Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Functional analysis of novel mutations in y(+)LAT-1 amino acid transporter gene causing lysinuric protein intolerance (LPI).

J. Mykkanen, D. Torrents, M. Pineda, M. Camps, Y. ME, N. Horelli-Kuitunen, K. Huoponen, M. Heinonen, J. Oksanen, O. Simell, S. ML, A. Zorzano, M. Palacín, and P. Aula
Chimera type domain decomposition methods applied to fractional step finite element

M. Vázquez, G.. Houzeaux, and R. Codina
Validation of Dimemas communication model for MPI collective operations

S. Girona, J. Labarta, and R. M. Badia

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