Agenda

Mostrant 11 - 13 de 13
  • 05 Mar 2024

    SORS: "Reinventing virtual memory for modern hardware"

    Formació
    Localització: [ONSITE] Severo Ochoa Room, Capella, BSC
    Enregistrar-se 2024-03-05 11:00:00 2024-03-05 11:00:00 Europe/Madrid SORS: "Reinventing virtual memory for modern hardware" For details, click on the following event link: https://www.bsc.es/ca/research-and-development/research-seminars/sors-reinventing-virtual-memory-modern-hardware [ONSITE] Severo Ochoa Room, Capella, BSC
  • 05 Dec 2023

    SORS/WomenInBSC: "A dynamic task scheduling method based on run-time information from the Miss Status Holding Register (MSHR) tables"

    Formació
    Localització: Sala P2 B at Til·lers Building and online via Zoom  
    Enregistrar-se 2023-12-05 12:00:00 2023-12-05 12:00:00 Europe/Madrid SORS/WomenInBSC: "A dynamic task scheduling method based on run-time information from the Miss Status Holding Register (MSHR) tables" For details, click on the following event link: https://www.bsc.es/ca/research-and-development/research-seminars/sorswomeninbsc-dynamic-task-scheduling-method-based-run-time-information-the-miss-status-holding Sala P2 B at Til·lers Building and online via Zoom  
  • 24 Nov 2023

    SORS: "A Potpourri of Ideas and Results in DRAM, FPGA Infrastructures, and RISC-V Processors"

    Localització: Room 2-1-17, Main building at BSC and onlive via Zoom
    Enregistrar-se 2023-11-24 11:00:00 2023-11-24 11:00:00 Europe/Madrid SORS: "A Potpourri of Ideas and Results in DRAM, FPGA Infrastructures, and RISC-V Processors" For details, click on the following event link: https://www.bsc.es/ca/research-and-development/research-seminars/sors-potpourri-ideas-and-results-dram-fpga-infrastructures-and-risc-v-processors Room 2-1-17, Main building at BSC and onlive via Zoom

Pàgines

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