Linearly Arranged Complete Interconnection Networks

 Status:
Published
 Publication number:
WO2024126481
 Priority date:
 Inventor:
Mateo Valero CortesJulio Ramon Beivide Palacio,  Cristóbal Camarero Coterillo,  Carmen Martínez Fernández,  Enrique Vallejo Gutiérrez
 Applicant:
Universidad de Cantabria, Barcelona Supercomputing Center - Centro Nacional de Supercomputación

Abstract

A design methodology that proposes specific deployments (or layouts) for the wires used by different interconnection networks employed in different HPC systems. It facilitates the design, packaging and deployment of HPC systems with interconnection network topologies such as Dragonflies, Dragonflies +, multi-dimensional Flattened Butterflies and HyperX, and all those networks whose topology uses, or is based on, complete graphs.