Francisco Javier Cazorla Almeida

2009

• Hardware Support for WCET Analysis of Multicore Systems

  M. Paolieri, E. Quinones, F. Cazorla, G. Bernat, and M. Valero
• ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs

  C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero
• Efficient Execution of Mixed Application Workloads in a Hard Real-Time

  M. Paolieri, E. Quinones, F. Cazorla, and M. Valero
• Characterizing the resource-sharing levels in the UltraSPARC T2 Processor

  V. Cakarevic, P. Radojkovic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero

2008

• A Two-Level Load/Store Queue Based on Execution Locality

  The 35th International Symposium on Computer Architecture (ISCA 2008)

  M. Pericas, A. Cristal, F. Cazorla, R. González, A. Veidenbaum, D. A. Jiménez, and M. Valero
• Dynamic Cache Partitioning Based on the MLP on Cache Misses.

  Transactions on HiPEAC

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors.

  International Conference on Parallel Processing (ICPP)

  C. Acosta, F. Cazorla, A. Ramirez, and M. Valero
• Scheduling Real-Time Systems With Explicit Resource Allocation Processors

  C. Boneti, F. Cazorla, R. Gioiosa, and M. Valero
• Understanding the overhead of the spin-lock loop in CMT architectures

  V. Cakarevic, P. Radojkovic, J. Verdú, A. Pajuelo, R. Gioiosa, F. Cazorla, M. Nemirovsky, and M. Valero
• A two-level Load/Store Queue based on Execution Locality

  M. Pericas, R. González, F. Cazorla, A. Cristal, A. Veidenbaum, D. A. Jiménez, and M. Valero