Accelerators and Communications for HPC (AccelCom)

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Our team drives leading-edge research and development around 3 main pillars: (1) Accelerators/coprocessors in HPC, (2) Programmability of heterogeneous memory systems, and (3) Inter-node communications. We collaborate closely with the major accelerator/coprocessor and network vendors for HPC: NVIDIA, Intel, and Mellanox. We run the BSC/UPC NVIDIA GPU Center of Excellence and collaborate with the Intel-BSC Exascale Lab. activities. We organize locally international events such as the PUMPS+AI Summer School, PATC Courses on CUDA/OpenACC and use of heterogeneous memory systems, and the Annual BSC/UPC HPC and MareNostrum hackathons, and collaborate in the organization of related international conferences and workshops such as SC, IEEE Cluster, or AsHES.

Objectives

Our broad mission is driving top-notch research and development around accelerators and communications technology for HPC. This can be framed in three main points:

  • Helping vendors advance their hardware architecture and software stack.
  • Designing and developing programming models, runtime systems, and libraries supporting accelerated computing and networking.
  • Developing and porting coprocessor-accelerated and distributed-memory applications.