Vector Processing Unit (VPU)

Co-Processors RISC-V BSC Group: Computer Sciences Hardware

The Vitruvius Vector Processing Unit (VPU), following called Vitruvius, is a RISC-V decoupled vector accelerator with lightweight out-of-order execution capabilities.

Software Author: 

Francesco Minervini, Oscar Palomar, Abraham Ruiz, Josué Quiroga, César Hernández, Alberto González, Carlos Rojas, Jonnatan Mendoza, Iván Vargas, Julián Pavón, Enrico Reggiani, Mustapha Bouhali, Lina Khoirunisya, Osman Unsal, Adrián Cristal, Mate Kovac, Leon Dragic, Mario Kovac, Abdallah Cheikh, Marco Meuli, Cristóbal Ramírez, Joan Marimon, Roger Figueras, Joan Cabre, Francesc Moll, And Mauro Olivieri, Mateo Valero

Contact:

francesco.minervini@bsc.es

License: 

Dual License

Primary tabs

Vitruvius targets high-performance computing (HPC) applications and is compliant with the RISC-V Vector extension 1.0 (RVV-1.0). The vector accelerator is highly parametrized which allow its implementation to instantiate a certain number of parallel execution pipelines (vector lanes), interconnected through a low-power area-efficient interconnect. The number of parallel lanes, as well as the maximum hardware-supported vector length, is an implementation parameter which can be freely set to target different application domains.

It may be used for High Performance Computing Applications as well as highly data-parallel applications.