SORS: Integrating posit arithmetic into a RISC-V core

In this work, we introduce PERCIVAL, an application-level posit RISC-V core based on CVA6, which enables native execution of all posit instructions, including quire fused operations. Unlike previous efforts, PERCIVAL overcomes the limitations of partial posit support or software emulation, achieving full hardware integration of the complete posit instruction set. To enhance the adoption of posit representation and facilitate its usage in software development, we have incorporated a RISC-V extension for posit instructions into LLVM. FPGA and ASIC syntheses demonstrate the hardware cost of 32-bit posits, emphasizing the overhead of a quire accumulator. However, our evaluation shows significant accuracy improvements in dot products and general matrix multiplications, reducing accuracy errors by up to four orders of magnitude. Remarkably, these accuracy benefits come with no compromise in execution speed, with posits performing as fast as single-precision floats and even outperforming double-precision floats in timing.