Speaker: Juan Cebrián, Norwegian university of science and technology NTNU
Abstract: Energy efficiency has recently replaced performance as the main design goal for microprocessors across all market segments. Vectorization, parallelization, specialization, heterogeneity and power saving mechanisms are the key approaches that both academia and industry embrace to make energy efficiency a reality. This presentation will focus on the effects of vectorization, parallelization and power saving mechanisms on energy efficiency.
More specifically:
- We show how to measure/estimate energy measurements in real hardware.
- We show how architects may overestimate the impact of certain techniques and underestimate others when using benchmarks that lack support for key common features.
- We introduce the ParVec benchmark suite, an extension to the Parsec benchmark suite to serve as a new baseline for evaluation of SIMD-capable computer systems.
- We briefly introduce the most common power saving mechanisms.
- We discuss mechanisms to force processors to adapt to power constraints in single-core, multi-core and 3D-stacked architectures with minimal performance impact.
Bio: Juan M. Cebrian. Born in Albacete, Spain, in 1982. Got his B.Sc in Computer Engineering on July 2006 (University of Murcia), M.Sc in July 2007 (University of Murcia) and finished his Ph.D on September 2011 (University of Murcia) funded by a four year grant from the Spanish Ministry of Education followed by a two-year Postdoc at the Norwegian University of Science and Technology (NTNU). Over the past few years, Cebrian has published more than 8 international journal papers and more than 16 conferences. Currently, his research focuses on the design of energy efficient heterogeneous multicores and SIMD technologies.