Miquel Moreto

- MIQUEL MORETO
- Position: HIGH PERFORMANCE DOMAIN-SPECIFIC ARCHITECTURES GROUP MANAGER
- Computer Sciences - High Performance Domain-Specific Architectures
- email: miquel [dot] moreto [at] bsc [dot] es
- Tel: +34 934137994

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Showing 81 - 90 results of 104

2011

Simulating Whole Supercomputer Applications

IEEE Micro

J. González, J. Giménez, M. Casas, M. Moreto, A. Ramirez, J. Labarta, and M. Valero

2010

ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, and M. Valero
Hard Real-Time Capable Multicore Processors for Space Applications

M. Moreto, M. Paolieri, J. Abella, E. Quinones, F. Cazorla, and M. Valero
Load Balancing Using Dynamic Cache Allocation

M. Moreto, F. Cazorla, R. Sakellariou, and M. Valero
Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies

K. Kedzierski, M. Moreto, F. Cazorla, and M. Valero
FlexDCP: a QoS framework for CMP architectures

ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors

M. Moreto, F. Cazorla, A. Ramirez, R. Sakellariou, and M. Valero

2009

pseudo-LRU based Cache Partitioning Algorithms

K. Kedzierski, M. Moreto, F. Cazorla, and M. Valero
CPU accounting in CMP Processors

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero
FlexDCP: a QoS framework for CMP architectures

ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors

M. Moreto, F. Cazorla, A. Ramirez, R. Sakellariou, and M. Valero
ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero

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