• Roberto Giorgi is an Associate Professor at Dept. of Information Engineering, University of Siena, Italy.

• He has received the eligibility (Italian National Abilitation) as Full-Professor since 30th March 2018.

• For one year, he was Research Associate at the University of Alabama in Huntsville, USA.

• He received his PhD in Computer Engineering and his MS in Electronics Engineering, Summa cum Laude both from University of Pisa, Italy.

• He coordinated the European Project AXIOM (3.9Meuro cost, 2015-2018, 7 partners), about designing and manufacturing the next generation board for Cyber-Physical Systems.

• He coordinated the TERAFLUX project (8.5Meuro cost, 2010-2014, 11 partners) in the area of Future and Emerging Technologies for Teradevice Computing.

• He is member of the HiPEAC Network of Excellence (High Performance Embedded-system Architecture and Compilation) since 2004.

• HewasDeputySteering Committee in the HiPEAC, Application leader in the ERA project (Embedded Reconfigurable Architectures), participated to SARC (Scalable ARChitectures) and attracted more than 3 Million Euro of Research Funding to the University of Siena in the last decade.

• He took part in ChARM project, developing software for performance evaluation of ARM-processor based embedded systems with cache memory for VLSI Inc.

• He has been IEEE Judge for the IEEE-CSIDC (Computer Society International Design Competition).

• He led the project ”Bluesign Translator”, which received a 5th worldwide prize by IEEE and top companies, and received the FORUM-P.A. prize by the Italian Ministry of Technological and Scientific Innovation, as absolute winner in the category of “actions for the social integration of disadvantaged people through ICT”.

• He has been selected by the European Commission as an independent expert for evaluating several ICT and HPC European Projects.

• He is co-author of more than 160 scientific papers.

• He is Ministry-appointed deputy and director for Uni.Siena in the National Consortium for Informatics (CINI).

• His current interests include Computer Architecture themes such as Embedded Systems, Multiprocessors, Memory System Performance, Workload Characterization, Reconfigurable Computing, High-Performance Computing.

• He is a Lifetime member of ACM and a Senior Member of the IEEE, IEEE Computer Society.
FULL CV HERE: https://www3.diism.unisi.it/~giorgi/cv.pdf

• PhD in “Information Engineering: Electronics, Informatics, Telecom.” University of Pisa, Pisa, Italy Oct. 1995-Sept. 1998 “Evaluation of a Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Multithreaded Multiprocessors” Thesis advisor: Prof. Cosimo Antonio Prete

• MEng in “Electronics Engineering” University of Pisa, Pisa, Italy “Performance Evaluation of Multiprocessor Systems, based on Real Traces Analysis” Thesis advisor: Prof. Cosimo Antonio Prete Mark: Summa cum Laude (110/110+Laude)

R26. 2024-25 Role: Coordinator(PI) (ICSC- Italian Center for Super-Computing), “EDGE-ME- Data-Driven Methodologies for the Management of High-Performance Parallel Applications on Heterogeneous Architectures for EdgeComputing”, (EUR 303’920 total funding, EUR 150’000 for UNISI).

R25. 2024-25 Role: Partecipant (ICSC- Italian Center for Super-Computing), “GEANT-HPC- Development and Optimization of GEANT4 for Space Experiments”, (EUR 155’261 total funding, EUR 155’261 for UNISI).

R24. 2023-26 Role: Local PI (Horizon-Europe and Italian Ministry for Made in Italy), “BIREX plus plus- European Digital Innovation Hub”, (EUR 5’995’583 total funding, EUR 114’383 for UNISI)- got Seal of Excellence. 

R23. 2023-25 Role: HPC Leader (National Plan for Recovery and Resilience (PNRR)), “SAILS- Siena infrastructure for Artificial Intelligence and Life Science”, (EUR 11’993’869 total funding, EUR 5’876’995 for UNISI)- ranked f irst among 25 projects, awarded but not executed.

R22. 2022-24 Role: Coordinator(PI) (Regione Toscana FSC), “High-Performance Artificial Intelligence Hardware Library”- DD21607/21 , (EUR 60’000 total funding, EUR 60’000 for UNISI).

R21. 2021-22 Role: Coordinator(PI) (Quest-IT), “Visualization of Signs for the Deaf by an Avatar”, (EUR 30’000 total funding, EUR 30’000 for UNISI).

R20. 2015-2018 Role: Coordinator(PI) (European Commission- H2020), “AXIOM: Agile, eXtensible, fast I/O Module for the cyber-physical era”- project id. 645496, (EUR 3’945’937 total funding, EUR 985’000 for UNISI)- Selection Mark: 14.5/15.

R19. 2015-2018 Role: Workpackage Leader WP7 “Evaluation and Design Space Exploration” (European Commission- H2020), “AXIOM: Agile, eXtensible, fast I/O Module for the cyber-physical era”- project id. 645496.

R18. 2012-2014 Role: Coordinator(PI) (European Commission- Special FP7-FET objective for cooperating with non-EU partners), Future and Emerging Technologies- Large Project- TERAFLUX–INCO “Exploiting Dataflow Parallelism in Teradevice Computing in cooperation with University of Delaware, USA”- project id. 309229, (EUR 420’000 total funding, EUR 150’000 for UNISI)- Selection Mark: 15/15.

R17. 2010-2014 Role: Workpackage Leader WP1 “Integration activities between TERAFLUX and UD” (European Commission- FP7-FET), Future and Emerging Technologies- Large Project- “TERAFLUX– Exploiting Dataflow Parallelism in Teradevice Computing in cooperation with University of Delaware, USA”- project id. 309229.

R16. 2010-2014 Role: Coordinator(PI) (European Commission- FP7-FET), TERAFLUX: “Exploiting Dataflow Parallelism in Teradevice Computing” project id. 249013, (EUR 5’700’000 total funding, EUR 1’167’000 for UNISI)- Selection Mark: 15/15.

R15. 2010-2014 Role: Workpackage Leader WP7 “Common Simulation and Compilation Platform” (European Commission- FP7-FET), “TERAFLUX– Exploiting Dataflow Parallelism in Teradevice Computing” project id. 249013.

R14. 2010-2013 Role: Workpackage Leader WP1 “Embedded Application Analysis” (European CommissionFP7-ICT), ERA: “Embedded Reconfigurable Architecture”- project id. 249059, (EUR 2’800’000 total funding, EUR 417’000 for UNISI).

R13. 2010-2014 Role: Participation (HiPEAC networking funding), HIPEAC3: “High-Performance Embedded Architecture and Compilation”, (EUR 4’000 total funding, EUR 4’000 for UNISI).

R12. 2008-2009 Role: Coordinator(PI) (Monte dei Paschi di Siena Foundation), “Integration of Sign Language for the Deaf in the digital television”, (EUR 50’000 total funding, EUR 50’000 for UNISI).

R11. 2007-2008 Role: Coordinator(PI) (Regione Toscana- through National Association of the Deaf), “Extension of the digital vocabulary of an automated Sign Language System for the Deaf”, (EUR 10’000 total funding, EUR 10’000 for UNISI).

R10. 2008-2012 Role: Participation (HiPEAC networking funding), HiPEAC Network of Excellence HIPEAC2: “HighPerformance Embedded Architecture and Compilation”, (EUR 5’000 total funding, EUR 5’000 for UNISI).

R9. 2008 Role: Coordinator of HiPEAC research cluster (HiPEAC seed funding), HiPEAC Network of Excellence “Multithreaded Dataflow Architectures”, (EUR 10’240 total funding, EUR 10’240 for UNISI).

R8. 2008 Role: Coordinator of HiPEAC research cluster (HiPEAC seed funding), “Cache implications of nonblocking thread execution in a multithreaded architecture”, (EUR 14’000 total funding, EUR 14’000 for UNISI).

R7. 2005-2009 Role: Participation (European Commission- FP6-FET), Future and Emerging Technologies- Integrated Project (IP) SCALA/SARC: “Scalable ARChitectures”, (EUR 8’500’000 total funding, EUR (through University of Pisa) 90’000 for UNISI).

R6. 2006 Role: Coordinator of HiPEAC research cluster (HiPEAC seed funding), HiPEAC Network of Excellence “Scalable Multicore Architectures” in Cooperation with Universities of Goteborg-Chalmers (Sweden), Delft-TUD (Netherlands), Barcelona-UPC (Spain), (EUR 30’000 total funding, EUR 10’000 for UNISI).

R5. 2004-2008 Role: Deputy Steering Committee (European Commission- FP6-NoE), HiPEAC Network of Excellence “High-Performance Embedded Architecture and Compilation”, coordination: Polytechnic University of Catalonia, Spain (UPC), (EUR 3’900’000 total funding, EUR n/a for UNISI).

R4. 2004-2005 Role: Coordinator(PI) (Italian Investment Fund for Basic Research (FIRB), Italian Ministry of Education, University and Research (MIUR)), “Innovative Architectures for High Performance Processors”, (EUR 60’000 total funding, EUR 30’000 for UNISI).

R3. 2004 Role: Coordinator(PI) (Monte dei Paschi di Siena Foundation), “Study and Realization of a Multimedia System for Translating and Communicating with the Sign Language for the Deaf”, (EUR 40’000 total funding, EUR 40’000 for UNISI).

R2. 2004-2005 Role: Coordinator(PI) (University Research Plan (PAR) of the University of Siena), “Innovative Architectures for Multimedia Applications in Embedded Systems”, (EUR 15’000 total funding, EUR 15’000 for UNISI).

R1. 2003-2005 Role: Participation (Italian Investment Fund for Basic Research (FIRB), Italian Ministry of Education, University and Research (MIUR)), “Reconfigurable Platforms for Broadband Mobile Devices”, activity of “Development of Innovative Cryptographic Techniques”, coordinator prof. Enrico Martinelli, (EUR 320’000 total funding, EUR 80’000 for UNISI).

• He is a Lifetime member of ACM and a Senior Member of the IEEE, IEEE Computer Society.

• 2021-presentScientificRepresentativeoftheUniversityofSienaintheRISC-VFoundation.

• 2021-presentGoverningBoardMemberofthe“CINI-HPC:KeyTechnologiesandTools”NationalLabfor High-PerformanceComputingKeyTechnologiesandTools.

• 2021-presentGoverningBoardMemberofthe“CINI-EmbeddedSystemsandSmartManufacturing”National LabforEmbeddedSystemsandSmartManufacturing.

• 2018-presentDirectoroftheUNISIResearchUnitofthe“CINI”coordinatingactivitiesofthelocalnodeand re-electedforthesecondterm.

• 2024-2025ScientificCoordinatoroftheICSC“EDGE-MEproject”coordinatingtheactivities.

• 2024-2025ScientificCoordinatoroftheQuest-IT“BS5project”coordinatingtheactivities.

• 2022-2024ScientificCoordinatoroftheRegioneToscana“HIPERAIHLproject”coordinatingtheactivities.

• 2015-2018ScientificCoordinatorof theEU“AXIOMproject”coordinatingtheactivitiesofmore than40 researchersacrossEurope.

• 2010-2014ScientificCoordinatoroftheEU“TERAFLUXproject”coordinatingtheactivitiesofmorethan100 researchersacrossEurope.

• 2010-2014ScientificCoordinatoroftheEU“TERAFLUX-INCOproject”coordinatingtheactivitiesofEU-USA collaboration.

• 2008-2009ScientificCoordinatoroftheFondazioneMPSproject: IntegrationofSignLanguagefortheDeaf in thedigital television.

• 2007-2008ScientificCoordinatorof theRegioneToscanaproject:Digital vocabularyof anautomatedSign LanguageSystemfortheDeaf.

• 2008-2008ScientificCoordinatorof theHiPEACresearchprojet:Cache implicationsofnonblockingthread executioninamultithreadedarchitecture. 29

• 2008-2008 Scientific Coordinator of the HiPEAC research project: Multithreaded Dataflow Architectures.

• 2006-2006 Scientific Coordinator of the HiPEAC research project: Scalable Multicore Architectures.

• 2004-2005 Scientific Coordinator of the FIRB (Scalable Multicore Architectures) project: Innovative Architectures for High Performance Processors.

• 2004-2005 Scientific Coordinator of the Fondazione MPS project: Study and Realization of a Multimedia System for Translating and Communicating with the Sign Language for the Deaf.

• 2004-2005 Scientific Coordinator of the UNISI project Innovative Architectures for Multimedia Applications in Embedded Systems.

• 2015-2018 WP-Leader AXIOM-WP7- Evaluation and Design Space Exploration.

• 2010-2014 WP-Leader TERAFLUX-WP7- Common Simulation and Compilation Platform.

• 2010-2014 WP-Leader TERAFLUX-INCO-WP1- Integration activities between TERAFLUX and UD.

• 2010-2014 WP-Leader ERA-WP1- Common Simulation and Compilation Platform.

• 2001-2009 Technological Area Coordinator for Master in New Technologies and Company Management (University of Siena).

• 2007-present co-responsible of the “Computer Architecture Lab”, with more than 30 workstations, major computing facilities and having equipment and donations from “AMD”, “HP-Labs”, “Intel”, “NVIDIA”, ”SECO“, “STMicroelectronics”, “Xilinx”.

ThefollowingcourseshavebeentaughtattheUniversityofSienaattheSchoolofEngineering,attheSchoolofEconomics andattheS.ChiaraCollege.Fromyear2000untilnow,morethan425ECTScredits1havebeentaught(correspondingto anaverageofabout17creditsperyear). . AsAssociateProfessor: Year Course ECTScredits Level School Lang. 2024-2025 AdvancedComputerArchitecture 9 Master InformationEng. English 2024-2025 ComputerArchitecture 6 Bachelor InformationEng. Italian 2023-2024 AdvancedComputerArchitecture 9 Master InformationEng. English 2023-2024 ComputerArchitecture 6 Bachelor InformationEng. Italian 2022-2023 ParallelProgrammingFundamentals 2 Ph.D. ItalianHPCSum.School English 2022-2023 AdvancedComputerArchitecture 9 Master InformationEng. English 2022-2023 ComputerArchitecture 6 Bachelor InformationEng. Italian 2021-2022 ParallelProgrammingFundamentals 3 Ph.D. SmartComputing English 2021-2022 AdvancedComputerArchitecture 9 Master InformationEng. English 2021-2022 ComputerArchitecture 6 Bachelor InformationEng. Italian 2020-2021 AdvancedComputerArchitecture 9 Master InformationEng. English 2020-2021 ComputerArchitecture 6 Bachelor InformationEng. Italian 2019-2020 AdvancedComputerArchitecture 9 Master InformationEng. English 2019-2020 ComputerArchitecture 6 Bachelor InformationEng. Italian 2018-2019 AdvancedComputerArchitecture 9 Master InformationEng. English 2018-2019 ComputerArchitecture 6 Bachelor InformationEng. Italian 2017-2018 AdvancedComputerArchitecture 9 Master InformationEng. English 2017-2018 ComputerArchitecture 6 Bachelor InformationEng. Italian 2016-2017 AdvancedComputerArchitecture 9 Master InformationEng. English 2016-2017 ComputerArchitecture 6 Bachelor InformationEng. Italian 2015-2016 AdvancedComputerArchitecture 9 Master InformationEng. English 2015-2016 ComputerArchitecture 6 Bachelor InformationEng. Italian 2014-2015 AdvancedComputerArchitecture 9 Master InformationEng. English 2013-2014 AdvancedComputerArchitecture 9 Master InformationEng. English 2013-2014 ComputerArchitecture 6 Bachelor InformationEng. Italian 2012-2013 AdvancedComputerArchitecture 9 Master InformationEng. English 2012-2013 ComputerArchitecture 6 Bachelor InformationEng. Italian 2011-2012 AdvancedComputerArchitecture 9 Master InformationEng. Italian 2011-2012 ComputerArchitecture 6 Bachelor InformationEng. Italian 2010-2011 AdvancedComputerArchitecture 9 Master InformationEng. Italian 2010-2011 ComputerArchitecture 6 Bachelor InformationEng. Italian 2009-2010 AdvancedComputerArchitecture 6 Master InformationEng. Italian 2009-2010 ComputerArchitecture 6 Bachelor InformationEng. Italian 2008-2009 AdvancedComputerArchitecture 6 Master InformationEng. Italian 2008-2009 ComputerArchitecture 6 Bachelor InformationEng. Italian 2007-2008 LowPowerArchitectures 2 Ph.D. InformationEng. Italian 2007-2008 AdvancedComputerArchitecture 6 Master InformationEng. Italian 2007-2008 InformationSecurity 3 Master Manag.ofFinancial Inst. Italian 2007-2008 ComputerArchitecture 6 Bachelor InformationEng. Italian 2006-2007 LowPowerArchitectures 2 Ph.D. InformationEng. Italian 2006-2007 AdvancedComputerArchitecture 6 Master InformationEng. Italian 2006-2007 InformationSecurity 3 Master Manag.ofFinancial Inst. Italian 2006-2007 ComputerArchitecture 6 Bachelor InformationEng. Italian 2005-2006 AdvancedComputerArchitecture 6 Master InformationEng. Italian 2005-2006 InformationSecurity 3 Master Manag.ofFinancial Inst. Italian 2005-2006 ComputerArchitecture 6 Bachelor InformationEng. Italian . AsAssistantProfessor: Year Course ECTScredits Level School Lang. 2004-2005 AdvancedComputerArchitecture 6 Master InformationEngineering Italian 2004-2005 OperatingSystemsandSecurity 3 Master ManagementofFinancial Inst. Italian 2004-2005 ComputerArchitecture 6 Bachelor InformationEngineering Italian 1OneECTScreditcorrespondstoabout8(master)-10(bachelor)hoursofteachingand15-17additionalhoursofpersonalstudyofthestudent. 282003-2004 AdvancedComputerArchitecture 12 Master InformationEngineering Italian 2003-2004 C++ProgrammingLaboratory 2 Master InformationEngineering Italian 2003-2004 ProgrammingFundamentals 3 Master DigitalEconomyandE-business Italian 2003-2004 OperatingSystemsandSecurity 3 Master ManagementofFinancial Inst. Italian 2003-2004 ComputerArchitecture 6 Bachelor InformationEngineering Italian 2003-2004 InformaticsforIndustrialApplications 6 Bachelor InformationEngineering Italian 2002-2003 AdvancedComputerArchitecture 12 Master InformationEngineering Italian 2002-2003 ComputerArchitectureLaboratory 2 Master InformationEngineering Italian 2002-2003 ProgrammingFundamentals 3 Master DigitalEconomyandE-business Italian 2002-2003 OperatingSystemsandSecurity 3 Master ManagementofFinancial Inst. Italian 2002-2003 ComputerArchitecture 6 Bachelor InformationEngineering Italian 2002-2003 InformaticsforIndustrialApplications 6 Bachelor InformationEngineering Italian 2001-2002 AdvancedComputerArchitecture 12 Master InformationEngineering Italian 2001-2002 ComputerArchitectureLaboratory 2 Master InformationEngineering Italian 2001-2002 OperatingSystemsandSecurity 3 Master ManagementofFinancial Inst. Italian 2001-2002 ComputerArchitecture 6 Bachelor InformationEngineering Italian 2001-2002 InformaticsforIndustrialApplications 6 Bachelor InformationEngineering Italian 2001-2002 Databasemanagement 3 Bachelor ManagementofFinancial Inst. Italian 2000-2001 AdvancedComputerArchitecture 12 Master InformationEngineering Italian 2000-2001 Databasemanagement 3 Master ManagementofFinancial Inst. Italian 2000-2001 ComputerArchitecture 6 Bachelor InformationEngineering Italian 1999-2000 AdvancedComputerArchitecture 12 Master InformationEngineering Italian 1999-2000 ComputerArchitecture 6 Bachelor InformationEngineering Italian . InternationalTeaching Prof.Giorgiheldinvitedlectureson”Multi-CoreandMany-Corearchitectures”attheUniversityofTampere,Finland inOctober2013.