Sargantana

Cores RISC-V BSC Group: Computer Sciences Hardware

Sargantana constitutes the third generation of Lagarto processors, the first open-source chips developed in Spain, within the framework of the DRAC project (Designing RISC-V-based Accelerators for next generation Computers) and is one of the most academically advanced open-source chips in Europe. The new Sargantana presents better performance than its two predecessors and is the first processor in the Lagarto family to break the gigahertz barrier in working frquency.

It is a 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI (RV64GV).
Software Author: 
Víctor Soria-Pardos, Max Doblas-Font, Guillem López-Paradís, Gerard Candón Arenas, Narcís Rodas Quiroga, Xavier Carril Gil, Pau Fontova-Musté, Neiel Israel Leyva Santes, Arnau Bigas Soldevilla, Oscar Lostes Cazorla, Rubén Langarita Benítez, Lorién López Villellas, Lluc Alvarez Martí, Roger Figueras Bague, Carlos Rojas Morales, Joan Marimon Illana, David Aguiló Domínguez, Santiago Marco-Sola, Sergi Soler Arrufat, Miquel Moretó Planas, Francesc Moll Echeto
Contact:

miquel.moreto@bsc.es

License: 

Solderpad Hardware License (Version 2.1)

Primary tabs

Chip design companies can be interested in this linux-capable RISC-V core. This design is suitable for IoT and edge devices, including microcontrollers for real time applications.