Publications

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2006

Branch Predictor Guided Instruction Decoding

IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006)

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy

B. Slamat, D. Nicolaescu, A. Veidenbaum, and M. Valero
A Simple Speculative Load Control Mechanism for Energy Saving

T. Ramírez, M. Pajuelo, O. J. Santana, and M. Valero
Performance Analysis of Sequence Alignment Applications

IISWC, IEEE Internacional Symposium on Workload Characterization

F. Sánchez, E. Salami, A. Ramirez, and M. Valero
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors

T. Morad, U. Weiser, A. Kolodny, M. Valero, and E. Ayguade
A DRAM/SRAM Memory Scheme for Fast Packet Buffers

J. Vidal, M. March, L.. Cerdá, J. Corbal, and M. Valero
Predictable Performance in SMT processors: Synergy Between the OS and SMTs

IEEE Transactions on Computers

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Simulating and Modeling Secure Web Applications

Lecture Notes on Computer Science (LNCS), 6th International Conference on Computational Science (ICCS'06)

R. Nou, J. Guitart, and J. Torres
Supporting the Introduction of Autonomic Computing in Middleware

J. J. Caubet, K. Hogan, R. Nou, J. Labarta, and J. Torres
Performance Impact of the Grid Middleware

Engineering the Grid: Status and Perspective

D. Carrera, J. Guitart, V. Beltran, J. Torres, and E. Ayguade

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