Publications

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2007

MLP-aware dynamic cache partitioning

International Conference on Parallel Architectures and Compilation Techniques (PACT)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Explaining Dynamic Cache Partitioning Speed Ups

IEEE Computer Architecture Letters

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Online Prediction of Applications Cache Utility

International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors

1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero
Performance Impact of the Interconnection Network on MareNostrum Applications

1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007)

A. Ramirez, O. Prat, J. Labarta, and M. Valero
Performance Impact of Unaligned memory Operations in SIMD Extensions for Video CODEC Applications

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2007)

M. Álvarez, E. Salami, J. Labarta, and M. Valero
The need for self-managed access nodes in grid environments

R. Nou, F. Julià, and J. Torres
Web Customer Modeling for Automated Session Prioritization on High Traffic Sites

N. Poggi, T. Moreno, J L. Berral, R. Gavaldà, and J. Torres
Policy-based autonomous bidding for overload management in eCommerce websites

T. Moreno, N. Poggi, J L. Berral, R. Gavaldà, and J. Torres
Automatic Detection and Banning of Content Stealing Bots for E-commerce

N. Poggi, J L. Berral, T. Moreno, R. Gavaldà, and J. Torres

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