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2013

A Hard Real-time Capable Multi-core SMT Processor

ACM Trans. Embed. Comput. Syst.

M. Paolieri, J. Mische, S. Metzlaff, M. Gerdes, E. Quinones, S. Uhrig, T. Ungerer, and F. Cazorla
Timing Effects of DDR Memory Systems in Hard Real-time Multicore Architectures: Issues and Solutions

ACM Trans. Embed. Comput. Syst.

M. Paolieri, E. Quinones, and F. Cazorla
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

IEEE Transactions on Parallel and Distributed Systems

P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
Silicon-aware Distributed Switch Architecture for On-chip Networks

J. Syst. Archit.

A. Roca, C. Hernández, J. Flich, F. Silla, and J. Duato
Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Proceedings of the Conference on Design, Automation and Test in Europe

B. Maric, J. Abella, and M. Valero
Task Mapping in Rectangular Twisted Tori

Proceedings of the High Performance Computing Symposium

C. Camarero, E. Vallejo, C. Martinez, M. Moreto, and R. Beivide
to be removed

Design Automation Conference (DAC), 2013 50th ACM / EDAC / IEEE
Hybrid Dataflow/Von-Neumann Architectures

IEEE Transactions on Parallel and Distributed Systems

F. Yazdanpanah, C. Alvarez-Martinez, D. Jiménez-González, and Y. Etsion
FPGA-Based Prototype of the Task Superscalar Architecture

7th HiPEAC Workshop on Reconfigurable Computing (WRC2013)

F. Yazdanpanah, Jiménez-González, Daniel, C. Álvarez, Y. Etsion, and R. M. Badia
Accelerating an Application Domain with Specialized Functional Units

ACM Transactions on Architecture and Code Optimization

C. González-Álvarez, J. B. Sartor, C. Álvarez, D. Jiménez-González, and L. Eeckhout

Pages