Publications

Export results as:

Showing 5511 - 5520 results of 5704

2004

An Expert Assistant for Computer Aided Parallelization

G. Jost, R. Chun, H. Jin, J. Labarta, and J. Giménez
Generation of Simple Analytical Models for Message Passing Applications

G. Rodríguez, R. M. Badia, and J. Labarta
A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors

ACM Transactions on Architecture and Code Optimization

O. J. Santana, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Traffic Aggregation Impact on the Memory Performance of Networking Applications

J. Verdú, M. Nemirovsky, J. García, and M. Valero
Analysis of Traffic Traces for Stateful Applications

J. Verdú, J. García, M. Nemirovsky, and M. Valero
Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers

M. March, J. García, L.. Cerdá, and M. Valero
A Hybrid DRAM/SRAM Design for Fast Packet Buffers

J. García, M. March, L.. Cerdá, J. Corbal, and M. Valero
Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
A latency conscious SMT branch predictor architecture

International Journal of High Performance Computing and Networking (IJHPCN)

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors

International Journal of High Performance Computing and Networking (IJHPCN)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero

Pages