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2006

Kilo-instruction Processors, Runahead and Prefetching

T. Ramírez, M. Pajuelo, O. J. Santana, and M. Valero
Speculative Early Register Release

J. J. Alastruey, T. Monreal, V. Viñals, and M. Valero
Branch Predictor Guided Instruction Decoding

IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006)

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy

B. Slamat, D. Nicolaescu, A. Veidenbaum, and M. Valero
A Simple Speculative Load Control Mechanism for Energy Saving

T. Ramírez, M. Pajuelo, O. J. Santana, and M. Valero
Performance Analysis of Sequence Alignment Applications

IISWC, IEEE Internacional Symposium on Workload Characterization

F. Sánchez, E. Salami, A. Ramirez, and M. Valero
Scheduling Connections using System-Level Thread Priorities in Web Applications

XVII Jornadas de Paralelismo

J. Alonso, J. Guitart, and J. Torres
Monitoring and analyzing a Grid Middleware Node

R. Nou, F. Julià, D. Carrera, K. Hogan, J. J. Caubet, J. Labarta, and J. Torres
Experiences with Simulations - A Light and Fast Model for Secure Web Applications

12th International Conference on Parallel and Distributed Systems (ICPADS'06)

R. Nou, J. Guitart, D. Carrera, and J. Torres
Simulating and Modeling Secure Web Applications

Lecture Notes on Computer Science (LNCS), 6th International Conference on Computational Science (ICCS'06)

R. Nou, J. Guitart, and J. Torres

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