Publications

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2004

A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors

ACM Transactions on Architecture and Code Optimization

O. J. Santana, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Traffic Aggregation Impact on the Memory Performance of Networking Applications

J. Verdú, M. Nemirovsky, J. García, and M. Valero
Analysis of Traffic Traces for Stateful Applications

J. Verdú, J. García, M. Nemirovsky, and M. Valero
Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers

M. March, J. García, L.. Cerdá, and M. Valero
A Hybrid DRAM/SRAM Design for Fast Packet Buffers

J. García, M. March, L.. Cerdá, J. Corbal, and M. Valero
Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
Software and Hardware Techniques to Optimize Register File Utilization in VLIW

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
Register-constrained Modulo Scheduling

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
Initial Evaluation of Multimedia Extensions on VLIW Architectures

E. Salami, and M. Valero
Performance and Power Evaluation of Clustered VLIW Processors with Functional Units

M. Pericas, E. Ayguade, J. Zalamea, J. Llosa, and M. Valero

Pages