Publications

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2009

ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero
Efficient Execution of Mixed Application Workloads in a Hard Real-Time

M. Paolieri, E. Quinones, F. Cazorla, and M. Valero
Characterizing the resource-sharing levels in the UltraSPARC T2 Processor

V. Cakarevic, P. Radojkovic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
CPU accounting in CMP Processors

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero

2008

A Two-Level Load/Store Queue Based on Execution Locality

The 35th International Symposium on Computer Architecture (ISCA 2008)

M. Pericas, A. Cristal, F. Cazorla, R. González, A. Veidenbaum, D. A. Jiménez, and M. Valero
Dynamic Cache Partitioning Based on the MLP on Cache Misses.

Transactions on HiPEAC

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors.

International Conference on Parallel Processing (ICPP)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero
Scheduling Real-Time Systems With Explicit Resource Allocation Processors

C. Boneti, F. Cazorla, R. Gioiosa, and M. Valero
Multicore Resource Management

IEEE Micro

K. J. Nesbit, M. Moreto, F. Cazorla, A. Ramirez, M. Valero, and J. E. Smith
Architecture performance prediction using evolutionary artificial neural networks

P. A. Castillo, A. M. Mora, J J. Merelo, J L. Laredo, M. Moreto, F. Cazorla, M. Valero, and S. A. McKee

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