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2012

ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches

ACM/IEEE Great Lakes Symposium on VLSI

B. Maric, J. Abella, and M. Valero
PROARTIS: Probabilistically Analysable Real-Time Systems

ACM Transactions on Embedded Computing Systems

F. Cazorla, E. Quinones, T. Vardanega, L. Cucu-Grosjean, B. Triquet, E. D. Berger, J. Abella, F. Wartel, M. Houston, L. Santinelli, L. Kosmidis, C. Lo, and D. Maxim
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

IEEE Transactions on Parallel and Distributed Systems

P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
Characterizing Thread Placement in the IBM POWER7 Processor

IEEE International Symposium on Workload Characterization (IISWC-2013)

S. Manousopoulos, M. Moreto, R. Gioiosa, N. Koziris, and F. Cazorla
Making Data Prefetch Smarter: Adaptive Prefetching on POWER7

21st International Conference on Parallel Architectures and Compilation Techniques (PACT-2012)

V. Jiménez, R. Gioiosa, F. Cazorla, A. Buyuktosunoglu, P. Bose, and F. P. O'Connell
Measurement-Based Probabilistic Timing Analysis for Multi-path Programs

24th Euromicro Conference on Real-Time Systems (ECRTS 2012)

L. Cucu-Grosjean, L. Santinelli, M. Houston, C. Lo, T. Vardanega, L. Kosmidis, J. Abella, E. Mezzetti, E. Quinones, and F. Cazorla
Optimal Task Assignment in Multithreaded Processors: A Statistical Approach

17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012)

P. Radojkovic, V. Cakarevic, M. Moreto, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
CPU Accounting for Multicore Processors

IEEE Transactions on Computers

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero
On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-Critical Environments

ACM Transactions on Architecture and Code Optimization

P. Radojkovic, S. Girbal, A. Grasset, E. Quinones, S. Yehia, and F. Cazorla
SMT Malleability in IBM POWER5 and POWER6 Processors

IEEE Transactions on Computers

A. Morari, C. Boneti, F. Cazorla, R. Gioiosa, C-Y. Cher, A. Buyuktosunoglu, P. Bose, and M. Valero

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