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2021

Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC

33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)

A. Serrano-Cases, J. M. Reina, J. Abella, E. Mezzetti, and F. J. Cazorla
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

K. Asifuzzaman, M. Abuelala, M. Hassan, and F. J. Cazorla
SAE Technical Paper Series On the Definition of Resource Sharing Levels to Understand and Control the Impact of Contention in Multicore Processors

Automotive Technical PapersSAE Technical Paper Series

H. Tabani, L. Kosmidis, E. Mezzetti, J. Abella, and F. J. Cazorla
Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

R. Pujol, H. Tabani, J. Abella, M. Hassan, and F. J. Cazorla
De-RISC: the First RISC-V Space-Grade Platform for Safety-Critical Systems

2021 IEEE Space Computing Conference (SCC)2021 IEEE Space Computing Conference (SCC)

N-J. Wessman, F. Malatesta, J. Andersson, P. Gomez, M. Masmano, V. Nicolau, J. Le Rhun, G. Cabo, F. Bas, R. Lorenzo, O. Sala, D. Trilla, and J. Abella
SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)

F. Bas, S. Alcaide, R. Lorenzo, G. Cabo, G. Gil, O. Sala, F. Mazzocchetti, D. Trilla, and J. Abella
SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)

O. Sala, S. Alcaide, G. Cabo, F. Bas, R. Lorenzo, P. Benedicte, D. Trilla, G. Gil, F. Mazzocchetti, and J. Abella
SafeSU: an Extended Statistics Unit for Multicore Timing Interference

2021 IEEE European Test Symposium (ETS)2021 IEEE European Test Symposium (ETS)

G. Cabo, F. Bas, R. Lorenzo, D. Trilla, S. Alcaide, M. Moretó, C. Hernandez, and J. Abella
Security, Reliability and Test Aspects of the RISC-V Ecosystem

2021 IEEE European Test Symposium (ETS)2021 IEEE European Test Symposium (ETS)

J. Abella, S. Alcaide, J. Anders, F. Bas, S. Becker, E. De Mulder, N. Elhamawy, F. K. Gurkaynak, H. Handschuh, C. Hernandez, M. Hutter, L. Kosmidis, I. Polian, M. Sauer, S. Wagner, and F. Regazzoni
Empirical Analysis of the Specialization of a Diversity Metric per Circuit Path (to appear)

SELSE 2021 17th Workshop on Silicon Errors in Logic - System Effects

S. Alcaide, H. Carles, and J. Abella

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