Publications

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2004

Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers

M. March, J. García, L.. Cerdá, and M. Valero
A Hybrid DRAM/SRAM Design for Fast Packet Buffers

J. García, M. March, L.. Cerdá, J. Corbal, and M. Valero
Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
Speculative Execution for Hiding Memory Latency

A. Pajuelo, A. González, and M. Valero
High Performance and Low Power VLIW for Numerical Applications

M. Pericas, E. Ayguade, J. Zalamea, J. Llosa, and M. Valero
Dynamic Memory Instruction Bypassing

D. Ortega, M. Valero, and E. Ayguade
Late Allocation and Early Release of Physical Registers

T. Monreal, V. Viñals, J. González, A. González, and M. Valero
Software and Hardware Techniques to Optimize Register File Utilization in VLIW

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
Register-constrained Modulo Scheduling

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
Initial Evaluation of Multimedia Extensions on VLIW Architectures

E. Salami, and M. Valero

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