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We are particularly interested for this role in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research. In instances of equal merit, the incorporation of the under-represented sex will be favoured.
We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.
If you consider that you do not meet all the requirements, we encourage you to continue applying for the job offer. We value diversity of experiences and skills, and you could bring unique perspectives to our team.
BSC Computer Architecture for Parallel Paradigms department is currently offering a research engineer position with a focus on RTL development of a Floating-Point Unit (FPU) for the HPC Digital Autonomy with RISC-V in Europe project or DARE. The DARE objectives are
- Contribute to European technological sovereignty by building a complete software/hardware ecosystem for HPC based on RISC-V, optimized for critical EU HPC applications by using a co-design approach.
- Produce a long-term roadmap with a critical timeline, milestones and all the necessary activities needed to build and deploy post-exascale systems in Europe using European technology.
- Deliver EU-owned, energy-efficient, high-end processors and accelerators designed for industrial-grade HPC and Cloud solutions.
- Design of floating-point arithmetic functional units for HPC and AI systems.
- Area and energy analysis and optimizations.
- Integration of FPU to Scalar Core and Vector Accelerator.
- Resolving bugs and working closely with the verification team to expand and improve the verification environment.
- Collaboration with the physical design team on synthesis experiments.
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Education
- BSc in Computer Science, Electronics or related.
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Essential Knowledge and Professional Experience
- 0-2 years of experience in design for ASIC.
- In-depth understanding of digital design for high-performance systems.
- Experience in SystemVerilog HDL.
- Experience with Verilator / VCS / QuestaSim.
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Additional Knowledge and Professional Experience
- Understanding of floating-point formats and arithmetic.
- Knowledge of IEEE-754 Standard.
- Experience with RISC-V IPs.
- Understanding of fixed-point arithmetic.
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Competences
- Fluency in spoken and written English.
- Ability to work both independently, within a team and in a multicultural environment.
- The position will be located at BSC within the Computer Sciences Department
- We offer a full-time contract (37.5h/week), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures
- Duration: Open-ended contract due to technical and scientific activities linked to the project and budget duration
- Holidays: 23 paid vacation days plus 24th and 31st of December per our collective agreement
- Salary: we offer a competitive salary commensurate with the qualifications and experience of the candidate and according to the cost of living in Barcelona
- Starting date: Month 0
All applications must be submitted via the BSC website and contain:
- A full CV in English, including contact details.
- A cover/motivation letter with a statement of interest in English, clearly specifying for which specific area and topics the applicant wishes to be considered. Additionally, two references for further contacts must be included. Applications without this document will not be considered.
Development of the recruitment process
The selection will be carried out through a competitive examination system ("Concurso-Oposición"). The recruitment process consists of two phases:
- Curriculum Analysis: Evaluation of previous experience and/or scientific history, degree, training, and other professional information relevant to the position. - 40 points
- Interview phase: The highest-rated candidates at the curriculum level will be invited to the interview phase, conducted by the corresponding department and Human Resources. In this phase, technical competencies, knowledge, skills, and professional experience related to the position, as well as the required personal competencies, will be evaluated. - 60 points. A minimum of 30 points out of 60 must be obtained to be eligible for the position.
The recruitment panel will be composed of at least three people, ensuring at least 25% representation of women.
In accordance with OTM-R principles, a gender-balanced recruitment panel is formed for each vacancy at the beginning of the process. After reviewing the content of the applications, the panel will begin the interviews, with at least one technical and one administrative interview. At a minimum, a personality questionnaire as well as a technical exercise will be conducted during the process.
The panel will make a final decision, and all individuals who participated in the interview phase will receive feedback with details on the acceptance or rejection of their profile.
At BSC, we seek continuous improvement in our recruitment processes. For any suggestions or comments/complaints about our recruitment processes, please contact recruitment [at] bsc [dot] es.
For more information, please follow this link.
BSC-CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.
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