Runtime aware architectures

The most common interpretation of Moore's Law is that the number of components on a chip and accordingly the computer performance doubles every two years. This experimental law has been holding from its first statement in 1965 until today. At the end of the 20th century, when clock frequencies stagnated at around 3GHz, and instruction level parallelism reached the phase of diminishing returns, industry turned towards multiprocessors, and thread level parallelism. However, too much of the technological complexity of multicore architectures is exposed to the programmers, leading to a software development nightmare that horrifies the entire computing industry.

The ERC-funded project Riding on Moore’s Law (RoMoL, GA 321253) proposes a radically new conception of parallel architectures, built using a higher level of abstraction. Instead of expressing algorithms as a sequence of instructions, we will group instructions into higher-level tasks that will be automatically managed by the architecture, much in the same way superscalar processors managed instruction level parallelism. RoMoL envisions a holistic approach where the parallel architecture is partially implemented as a software runtime management layer, and the reminder in hardware. The hardware gains the freedom to deliver performance at the expense of additional complexity, as long as it provides the required support primitives for the runtime software to hide complexity from the programmer. The OmpSs programming model together with the Mercurium compiler and the Nanos++ runtime, which are being intensively developed at the Barcelona Supercomputing Center (BSC-CNS), will provide the perfect environment for this approach (http://pm.bsc.es/).

This regained freedom in hardware design will enable to revisit a number of previously proposed architectural concepts in light of the new technology context for unforeseen impact in performance and energy efficiency. This now becomes possible thanks to the joint development of the runtime layer with the parallel architecture. This holistic approach towards parallel architectures offers a single solution that could solve most of the problems we encounter in the current approaches: handling parallelism, the memory wall, the power wall, and the upcoming reliability wall in a wide range of application domains from mobile up to supercomputers. RoMoL will tackle these crucial challenges for the next 5 years and will involve around 15 researchers, including PhD students, engineers, and post-doctoral researchers. RoMoL will facilitate collaborations with high level research visitors and maximize positive synergies between current research activities in the Computer Sciences Department at the BSC-CNS.

Altogether, this novel approach toward future parallel architectures is the way to ensure continued performance improvements, getting us out of the technological mess that computers have turned into, once more riding on Moore's Law.