RISC-V Summit Europe takes place in Munich from Monday 24th to Friday 28th June
BSC has strategically advanced research in RISC-V based open-source technologies in the field of HPC. It is contributing to strengthening the ecosystem in the areas of semiconductors and supercomputing by leveraging its software and hardware co-design approach for developments. The final aim is to impact into the society through research activities targeting providing novel solutions for fulfilling the exponential demanding requirements of scientific applications.
As the RISC-V ecosystem continues to grow and mature, BSC keeps with its commitment with the RISC-V European community as a Community Organization Member of RISC-V International. BSC hosted the first edition of the RISC-V Summit Europe (Barcelona, 2023). This year the center will also be present at booth 17 in the exhibition area, where visitors will be able to know more about the center, RISC-V@BSC initiatives and technologies, and meet our experts in person. In addition, on Monday BSC experts will participate to the technical work groups that are only open to members and, on Friday 28th June, BSC co-organized the side event titled 1st Open-Source RISC-V Software Workshop.
“I am pleased to observe a stronger presence of BSC at this year RISC-V Summit Europe. It serves as an excellent platform to interact with the community, learn more about others’ work, and also highlight the results of BSC research related to RISC-V”, says Teresa Cervero, BSC researcher and RISC-V Steering Committee member. She was also local organizer of the RISC-V Summit Europe 2023 edition.
Finally, BSC has compiled a dedicated BSC RISC-V Technologies Catalogue that includes its technologies and initiatives where BSC researchers are involved.
The overall programme with BSC participation can be summarized in the table below:
|
BSC contributor |
Session |
Time |
Area |
|
Tuesday, June 25th |
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|
Sergi Alcaide |
SafeGantana: A Lockstep In-Order RISC-V Core |
Breaks |
Poster A-09 |
|
Leonidas Kosmidis |
METASAT Platform: High Performance Space Processing for Institutional Missions Using Multicore, GPU and AI Accelerators |
Breaks |
Poster C-11 |
|
Wednesday, June 26th |
|||
|
Teresa Cervero |
RISC-V@BSC: Fostering RISC-V strategy in the EU through Research, Innovation & Education |
16:15 |
Plenary |
|
Ramon Canal |
Vitamin-V: Expanding Open-Source RISC-V Cloud Environments |
16:30 |
Plenary |
|
Teresa Cervero |
Panel: How can Europe engage more in RISC-V? |
17:15 |
Plenary |
|
Thursday, June 27th |
|||
|
Marc Grau |
Platform Orchestration with a RISC-V Tiny Controller |
Breaks |
Poster C-09 |
|
Leonidas Kosmidis |
RADLER: RISC-V Autonomous Driving LEvel fouR hardware/software co-design |
Breaks |
Poster D-07 |
|
Filippo Mantovani |
EPAC prototype demo |
TBC |
Demo Day |
|
Friday, June 28th |
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|
Ramon Canal, Aaron Call |
9 -17h |
Side Event |