Adria Armejach Sanosa

2011

• Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency

  21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11)

  A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero
• Circuit Design of a Dual-Versioning L1 Data Cache

  Integration The VLSI Journal

  A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero

2010

• ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance

  A. Armejach, A. Seyedi, R T. J. Gil, I. Hur, O. Unsal, A. Cristal, and M. Valero

2009

• EazyHTM: eager-lazy hardware transactional memory

  Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture

  S. Tomić, C. Perfumo, C. Kulkarni, A. Armejach, A. Cristal, O. Unsal, T. Harris, and M. Valero
• EazyHTM, Eager-Lazy Hardware Transactional Memory

  42nd International Symposium on Microarchitecture (MICRO)

  S. Tomić, C. Perfumo, C. Kulkarni, A. Armejach, A. Cristal, O. Unsal, T. Harris, and M. Valero