Publications

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2008

Parallel Scalability of H.264

1st Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG)

C. Meenderinck, A. Azevedo, M. Álvarez, B. Juurlink, and A. Ramirez
Memory Management on Chip-MultiProcessors with on-chip Memories

Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08)

I. Gelado, A. Ramirez, N. Navarro, and C. Villavieja
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications

Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08)

S. Isaza, F. Sánchez, G. N. Gaydadjiev, A. Ramirez, and M. Valero
A Dynamic Scheduler for Balancing HPC Applications

C. Boneti, R. Gioiosa, F. Cazorla, and M. Valero
Software-Controlled Priority Characterization of POWER5 Processor

International Symposium on Computer Architecture (ISCA)

C. Boneti, F. Cazorla, R. Gioiosa, C-Y. Cher, A. Buyuktosunoglu, and M. Valero
Balancing HPC Applications Through Smart Allocation of Resources in MT Processors

C. Boneti, F. Cazorla, R. Gioiosa, J. Corbalán, J. Labarta, and M. Valero
Task Management Analysis on the Cell BE

XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain)

A. Rico, A. Ramirez, and M. Valero
On-Chip memories, the OS perspective

5th HiPEAC Industrial Workshop

C. Villavieja, I. Gelado, A. Ramirez, and N. Navarro
Drug Design Issues on the Cell BE

H. Servat, X. Aguilar, C. González, D. Cabrera, and D. A. Jiménez
Vectorized AES Core for high-throughput secure environments

M. Pericas, R. Chaves, G. N. Gaydadjiev, M. Valero, and S. Vassiliadis

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