Publications

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2004

Throughput versus Quality of Service in SMT processors

Euromicro-DSD (Digital System Design)

E. Fernández, F. Cazorla, A. Ramirez, P. Knijnenburg, R. Sakellariou, and M. Valero
Speculative Execution for Hiding Memory Latency

A. Pajuelo, A. González, and M. Valero
High Performance and Low Power VLIW for Numerical Applications

M. Pericas, E. Ayguade, J. Zalamea, J. Llosa, and M. Valero
Dynamic Memory Instruction Bypassing

D. Ortega, M. Valero, and E. Ayguade
Late Allocation and Early Release of Physical Registers

T. Monreal, V. Viñals, J. González, A. González, and M. Valero
Software and Hardware Techniques to Optimize Register File Utilization in VLIW

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
Register-constrained Modulo Scheduling

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
Performance Impact of Using SSL on Dynamic Web Applications

XV Jornadas de Paralelismo

V. Beltran, J. Guitart, D. Carrera, J. Torres, E. Ayguade, and J. Labarta
Evaluating the Scalability of Java Event-Driven Web Servers

V. Beltran, D. Carrera, J. Torres, and E. Ayguade

2003

Ephemeral Registers with Multicheckpointing

A. Cristal, J. F. Martínez, J. Llosa, and M. Valero

Pages