Publications

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2008

Software-Controlled Priority Characterization of POWER5 Processor

International Symposium on Computer Architecture (ISCA)

C. Boneti, F. Cazorla, R. Gioiosa, C-Y. Cher, A. Buyuktosunoglu, and M. Valero
Balancing HPC Applications Through Smart Allocation of Resources in MT Processors

C. Boneti, F. Cazorla, R. Gioiosa, J. Corbalán, J. Labarta, and M. Valero
Task Management Analysis on the Cell BE

XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain)

A. Rico, A. Ramirez, and M. Valero
On-Chip memories, the OS perspective

5th HiPEAC Industrial Workshop

C. Villavieja, I. Gelado, A. Ramirez, and N. Navarro
Drug Design Issues on the Cell BE

H. Servat, X. Aguilar, C. González, D. Cabrera, and D. A. Jiménez
Vectorized AES Core for high-throughput secure environments

M. Pericas, R. Chaves, G. N. Gaydadjiev, M. Valero, and S. Vassiliadis
Virtual Private Machines: Hardware/Software Interactions in the Multicore Era

K. J. Nesbit, M. Moreto, F. Cazorla, A. Ramirez, M. Valero, and J. E. Smith
SLA-Driven Semantically-Enhanced Dynamic Resource Allocator for Virtualized Service Providers

4th IEEE International Conference on e-Science (e-Science 2008)

J. Ejarque, M. de Palol, Í. Goiri, F. Julià, J. Guitart, R. M. Badia, and J. Torres
Distributed Learning Mechanism Against Flooding Network Attacks

J L. Berral, J. Alonso, N. Poggi, R. Gavaldà, M. Parashar, and J. Torres
Self-Adaptive Utility-Based Web Session Management.

N. Poggi, T. Moreno, J L. Berral, R. Gavaldà, and J. Torres

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