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2008

Measuring Operating System Overhead on CMT Processors

P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, R. Gioiosa, F. Cazorla, M. Nemirovsky, and M. Valero
Multicore Resource Management

IEEE Micro

K. J. Nesbit, M. Moreto, F. Cazorla, A. Ramirez, M. Valero, and J. E. Smith
Architecture performance prediction using evolutionary artificial neural networks

P. A. Castillo, A. M. Mora, J J. Merelo, J L. Laredo, M. Moreto, F. Cazorla, M. Valero, and S. A. McKee
MLP-aware dynamic cache partitioning

2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Evolutionary system for prediction and optimization of hardware architecture performance

P. A. Castillo, J J. Merelo, M. Moreto, F. Cazorla, M. Valero, A. M. Mora, J L. Laredo, and S. A. McKee
Understanding the overhead of the spin-lock loop in CMT architectures

V. Cakarevic, P. Radojkovic, J. Verdú, A. Pajuelo, R. Gioiosa, F. Cazorla, M. Nemirovsky, and M. Valero
A two-level Load/Store Queue based on Execution Locality

M. Pericas, R. González, F. Cazorla, A. Cristal, A. Veidenbaum, D. A. Jiménez, and M. Valero
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

J. J. Alastruey, F. Cazorla, T. Monreal, V. Viñals, and M. Valero
Distributing Orthogonal Redundancy on Adaptive Disk Arrays

J L. González, and T. Cortes
The RAM Enhanced Disk Cache Project (REDCAP)

P. Gonález-Férez, J. Piernas, and T. Cortes

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