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2006

Runtime Address Space Computation for SDSM Systems

J. Balart, M. González, X. Martorell, E. Ayguade, and J. Labarta
Exploiting Multilevel Parallelism using OpenMP on a Massive Multithreaded Architecture

D. Ródenas, X. Martorell, E. Ayguade, J. Labarta, G. Almasi, C. Cascaval, J. Castaños, and J. Moreira
CellSs: A Programming Model for the Cell BE Architecture

P. Bellens, J. M. Pérez, R. M. Badia, and J. Labarta
Scaling MPI to short-memory MPPs such as BG/L

M. Farreras, T. Cortes, J. Labarta, and G. Almasi
Running OpenMP application efficiently on an everything-shared SDSM

J. Costa, T. Cortes, X. Martorell, E. Ayguade, and J. Labarta
Branch Predictor Guided Instruction Decoding

IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006)

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy

B. Slamat, D. Nicolaescu, A. Veidenbaum, and M. Valero
A Simple Speculative Load Control Mechanism for Energy Saving

T. Ramírez, M. Pajuelo, O. J. Santana, and M. Valero
Performance Analysis of Sequence Alignment Applications

IISWC, IEEE Internacional Symposium on Workload Characterization

F. Sánchez, E. Salami, A. Ramirez, and M. Valero
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors

T. Morad, U. Weiser, A. Kolodny, M. Valero, and E. Ayguade

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