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2004

Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors

10th International Conference on High Performance Computer Architecture (HPCA-10)

A. Falcón, A. Ramirez, and M. Valero
Reducing Fetch Architecture Complexity Using Procedure Inlining

8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT)

O. J. Santana, A. Ramirez, and M. Valero
A latency conscious SMT branch predictor architecture

International Journal of High Performance Computing and Networking (IJHPCN)

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors

International Journal of High Performance Computing and Networking (IJHPCN)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
DCache Warn: An I-Fetch Policy To Increase SMT Efficiency

18th International Parallel and Distributed Processing Symposium (IPDPS-2004)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
Dynamically Controlled Resource Allocation in SMT Processors

37th Annual International Symposium on Microarchitecture (MICRO-37)

F. Cazorla, A. Ramirez, M. Valero, and E. Fernández
QoS for High-Performance SMT Processors in Embedded Systems

IEEE Micro

F. Cazorla, A. Ramirez, M. Valero, P. Knijnenburg, R. Sakellariou, and E. Fernández
A Low Complexity Fetch Architecture for High Performance Superscalar Processors

ACM Transactions on Architecture and Compiler Optimizations (TACO)

M. Valero, O. J. Santana, A. Ramirez, and J. Lluis Larriba-Pey
Predictable Performance in SMT Processors

Computing Frontiers (CF'04)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero

Pages