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Motivation
The market for Critical Real-Time Embedded Systems (CRTES) is experiencing an unprecedented growth. The inclusion in CRTES of increasingly sophisticated value-added functions, such as for example Advanced Driver Assistance Systems, causes CRTES makers to continue to seek increasingly more guaranteed computation performance. CRTES designers also consider mixed-criticality solutions so that more functional value can be obtained per unit of product. Probabilistic techniques may greatly aid in this regard. In particular, with Measurement-Based Probabilistic Timing Analysis (MBPTA) methods the execution time of the application can be accurately modelled – at some level of execution granularity – by a probability distribution. MBPTA seeks to determine worst-case execution time (WCET) estimates for arbitrarily low probabilities of exceedance, termed probabilistic WCET or pWCET. Even if any pWCET may in principle be exceeded, this can only happen with a given probability, which can be determined at a level low enough for the application domain; for example, in the region of 10-15 per hour of operation, largely below the acceptable probability of failure in certified systems.
In the last few years, probabilistic timing analysis (PTA) in general, and MBPTA in particular, has emerged as a viable alternative to classic timing analysis approaches. Owing to its observation-based nature, MBPTA requires considerably less information on the detailed internal behaviour of the hardware and the software of the system, which is instead the crux of classic WCET methods. PTA has become an acknowledged area of scientific interest with an increasing number of active researchers and a good and rising score of publications. As a testimony to that, the last 2 RTSS editions (2012 and 2013) have had 1 paper in PTA and ECRTS 2014 has 4 papers on PTA related topics and a specific session on Probabilistic Methods. Furthermore, the Best Paper Award in the DAC 2014conference went to a PTA-related paper. There also is high industrial interest on PTA, sensed via direct and indirect participation in the PROXIMA project, which focuses on furthering PTA methods and technology for multicore and manycore processors.
This tutorial introduces attendees to Measurement-Based Probabilistic Timing Analysis (MBPTA) with emphasis on its properties from the end user point of view and its requirements on the underlying hardware and software platform. Through didactic material and several examples, the audience will be exposed to understanding MBPTA concepts. The tutorial also presents the current advances of MBPTA and the main challenges it has to address to be increasingly used by industry.
Level
Introductory. The audience should have basic knowledge on real-time systems and be familiar with basic concepts of WCET analysis, knowing the basic difference between static and measurement-based timing analysis. No prior knowledge on PTA is required.
Reasons for attending
The envisioned tutorial will cause benefits in two directions:
- Introducing researchers and industrial practitioners to the PTA requirements, benefits, and basic functioning. With PTA acknowledged as a fertile area of research, this part of the tutorial will allow participants to catch up with the essentials of PTA faster and to a greater depth.
- Expose participants to the latest advances in PTA for method, techniques and requirements on the hardware and the software of the system, with a view to how they compare to other techniques in the state of the art.
Presenters
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Francisco J. Cazorla is the leader of the CAOS research group at BSC and researcher in the Spanish National Research Council (IIIA-CSIC). Francisco has led several bilateral projects with industry: IBM, Sun Microsystems (now Oracle) and the European Space Agency. He also currently leads the PROXIMA FP7 STREP EU project. He has three submitted patents on the area of hard-real time systems. His research area focuses on multithreaded architectures for both high-performance and real-time systems on which he is co-advising ten PhD theses. He has co-authored over 80 papers in international refereed conferences. He spent five months as intern in IBM‘s T.J. Watson in New York in 2004. |
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Tullio Vardanega is at the University of Padua, Italy, since January 2002. He holds a master degree in Computer Science from the University of Pisa, Italy, and a PhD in Computer Science from the Technical University of Delft, Netherlands. He worked at European Space Agency Research and Technology Center from July 1991 to December 2001. At the University of Padua, he teaches and leads research in the areas of high-integrity distributed real-time systems and advanced software engineering methods. He has a vast network of national and international research collaborations. He has co-authored 90+ refereed papers and held organizational roles in several international events and bodies, for ESA, the European Commission, ISO, IEEE and Ada-Europe. |
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Jaume Abella is a senior PhD. Researcher in the CAOS group at BSC and member of HIPEAC. He worked at the Intel Barcelona Research Center from 2005 to 2009 in the low-level design and modelling of circuits and microarchitectures for fault-tolerance and low power, and led the group on memory hierarchies. Jaume authored 15 patents at Intel. He joined the BSC in 2009 where he is in charge of hardware designs for FP7 PROXIMA, BSC certification activities in VeTeSS, and involved in H2020 SAFURE and two ESA projects. He has authored more than 80 papers in top conferences and journals in the area. He has advised 6 PhD/master students and is co-advisor of 7 PhD/master students. |
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Mark Pearce is a Software Engineering specialist working with Rapita Systems Limited. He is currently actively involved in a number of research and development projects developing probabilistic timing analysis techniques and other timing solutions for multi-core architectures. Prior to this, he has gained extensive experience working on complex embedded real-time systems in a number of industry sectors including aerospace, defence and manufacturing. Whilst developing broad experience across the entire software life cycle, he has also specialized in the area of testing and integration. Mark gained a B.Eng degree studying Microelecronics and Microprocessor Applications and an MBA through study at Henley Management College. |