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2007

High Performance Embedded Architectures and Compilation Roadmap

K D. Bosschere, W. Luk, X. Martorell, N. Navarro, M. O'Boyle, D. Pnevmatikatos, A. Ramirez, P. Sainrat, A. Seznec, P. Stenström, and O. Temam
A Streaming Machine Description and Programming Model

7th Intl. Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VII)

P. Carpenter, D. Ródenas, X. Martorell, A. Ramirez, and E. Ayguade
Implementation and Validation of a Cell Simulator using UNISIM

3rd HiPEAC Industrial Workshop

A. Rico, F. Cabarcas, D. Ródenas, X. Martorell, A. Ramirez, and E. Ayguade
HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications

2007 IEEE International Symposium on Workload Characterization (IISWC-2007)

M. Álvarez, E. Salami, A. Ramirez, and M. Valero
Enlarging Instruction Streams

IEEE Transactions on Computers

O. J. Santana, A. Ramirez, and M. Valero
On the Problem of Minimizing Workload Execution Time in SMT Processors

International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
FAME: FAirly MEasuring Multithreaded Architectures

J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
Online Prediction of Throughput for Different Cache Sizes

XVIII Jornadas de Paralelismo

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
MLP-aware dynamic cache partitioning

International Conference on Parallel Architectures and Compilation Techniques (PACT)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Explaining Dynamic Cache Partitioning Speed Ups

IEEE Computer Architecture Letters

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero

Pages