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2013

Performance Analysis Techniques for the Exascale Co-Design Process

Proceedings of International Conference on Parallel Computing (PARCO)

M. Schulz, A. Bhatele, J. Belak, P. - T. Bremer, M. Casas, G. Bronevetsky, T. Gamblin, K. Isaacs, I. Laguna, J. Levine, V. Pascucci, D. Richards, and B. Rountree
Achieving Timing Composability with Probabilistic Timing Analysis

In IEEE International Symposium on Object-component-service-oriented Real-time distributed computing (ISORC)

L. Kosmidis, E. Quinones, J. Abella, T. Vardanega, and F. Cazorla
Fair CPU Time Accounting in CMP+SMT Processors

ACM Trans. Archit. Code Optim.

C. Luque, M. Moreto, F. Cazorla, and M. Valero
Addressing Link Degradation in NoC-Based ULSI Designs

Euro-Par 2012: Parallel Processing Workshops

C. Hernández, F. Silla, and J. Duato
PROARTIS: Probabilistically Analyzable Real-Time Systems

ACM Trans. Embed. Comput. Syst.

F. Cazorla, E. Quinones, T. Vardanega, L. Cucu, B. Triquet, G. Bernat, E. Berger, J. Abella, F. Wartel, M. Houston, L. Santinelli, L. Kosmidis, C. Lo, and D. Maxim
A Hard Real-time Capable Multi-core SMT Processor

ACM Trans. Embed. Comput. Syst.

M. Paolieri, J. Mische, S. Metzlaff, M. Gerdes, E. Quinones, S. Uhrig, T. Ungerer, and F. Cazorla
Timing Effects of DDR Memory Systems in Hard Real-time Multicore Architectures: Issues and Solutions

ACM Trans. Embed. Comput. Syst.

M. Paolieri, E. Quinones, and F. Cazorla
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

IEEE Transactions on Parallel and Distributed Systems

P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
Silicon-aware Distributed Switch Architecture for On-chip Networks

J. Syst. Archit.

A. Roca, C. Hernández, J. Flich, F. Silla, and J. Duato
Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Proceedings of the Conference on Design, Automation and Test in Europe

B. Maric, J. Abella, and M. Valero

Pages