Lagarto KA

Cores RISC-V Hardware

One of the main goals in processor design is achieving high performance. Various proposals from academia and industry have explored innovative ideas leveraging Moore's Law, balancing complexity and performance. SUperscalar processors execute multiple instructions per clock cycle, effectively using instruction-level parallelism, dynamic scheduling, efficient memory management, and specialized accelerators.

 

Software Author: 
Abraham Josafat Ruíz Ramírez, Alejandro Iznardo Ruiz, Ansub Zia Taimur, Carlos Rojas Morales, César Alejandro Hernández Calderón, Cristóbal Ramírez Lazo, David Anguiló Domínguez, Francesco Minervini, Iván Díaz Ortega, Ivan Vargas Valdivieso, Javier Salamero Sanz, Joan Cabre Olive, Jonatan Mendoza Escobar, Julián Pavón Rivera, Khan Salik Najeeb, Max Doblas Font, Miquel Roset Julia, Narcís Rodas Quiroga, Neiel Israel Leyva Santes, Pau Fontova Muste, Prashant Ahuja, Roberto Ignacio Genovese, Roger Fiueras Bague, Xavier Carril, Xavier Salvà Grimalt, Adrián Cristal, Francesc Moll, Miquel Moretó, Oscar Palomar, Osman Unsal, Marco Antonio Ramírez Salinas, Luis Alfonso Villa Vargas, José Antonio Flores Escobar, Mario Rodríguez, Marc Domínguez, Víctor Jiménez, Joan Marimon
Contacto:
License: 

Solderpad Hardware Licence (Version 2.1)

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DRAC aims to design, verify, and manufacture a high-performance processor with several accelerators in a system-on-chip (SoC). In collaboration between BSC and CIC-IPN, the Lagarto Ka processor has been proposed: a 2-way, 64-bit superscalar processor with a 12-stage out-of-order microarchitecture based on the RISC-V instruction set.

It may be used for embeddded systems. This design is suitable for IoT and edge devices, including microcontrollers for real time applications.