Petar Radojkovic

2020

• Cost-Aware Prediction of Uncorrected DRAM Errors in the Field

  International Conference for High Performance Computing, Networking, Storage, and Analysis (SC)

  I. Boixaderas, J. Bartolome, P. Carpenter, D. Zivanovic, D. Vicente, P. Radojkovic, S. More, M. Casas, and E. Ayguadé

2019

• DRAM Errors in the Field: A Statistical Approach

  The International Symposium on Memory Systems (MEMSYS 2019)

  D. Zivanovic, P. Esmaili-Dokht, S. More, J. Bartolome, P. Carpenter, P. Radojkovic, and E. Ayguadé

2018

• Mainstream vs. Emerging HPC: Metrics, Trade-offs and Lessons Learned

  30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2018)

  M. Radulovic, K. Asifuzzaman, D. Zivanovic, N. Rajovic, G. Colin de Verdière, D. Pleiter, M. Marazakis, N. Kallimanis, P. Carpenter, P. Radojkovic, and E. Ayguadé

2017

• Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNoDe approach

  Euromicro Symposium on Digital System Design, DSD 2017

  A. Rigo, C. Pinto, K. Pouget, D. Raho, D. Dutoit, P-Y. Martinez, C. Doran, L. Benini, I. Mavroidis, M. Marazakis, V. Bartsch, G. Lonsdale, A. Pop, J. Goodacre, A. Colliot, P. Carpenter, P. Radojkovic, D. Pleiter, D. Drouin, and B. Dupont de Dinechin
• Enabling a Reliable STT-MRAM Main Memory Simulation

  Proceedings of the Third International Symposium on Memory Systems (MEMSYS)

  K. Asifuzzaman, R. Sanchez Verdejo, and P. Radojkovic
• Main Memory in HPC: Do We Need More, or Could We Live With Less?

  ACM Transactions on Architecture and Code Optimization

  D. Zivanovic, M. Pavlovic, M. Radulovic, H. Shin, J. Son, S. A. McKee, P. Carpenter, P. Radojkovic, and E. Ayguade

2016

• Large-Memory Nodes for Energy Efficient High-Performance Computing

  Proceedings of the Second International Symposium on Memory Systems (MEMSYS '16)

  D. Zivanovic, M. Radulovic, G. Llort, D. Zaragoza, J. Strassburg, P. Carpenter, P. Radojkovic, and E. Ayguade
• Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC

  Proceedings of the Second International Symposium on Memory Systems (MEMSYS)

  K. Asifuzzaman, M. Pavlovic, M. Radulovic, D. Zaragoza, O. Kwon, K-C. Ryoo, and P. Radojkovic
• Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

  IEEE Transactions on Computers

  P. Radojkovic, P. Carpenter, M. Moreto, V. Cakarevic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero

2015

• Limpio: LIghtweight MPI instrumentatiOn

  Proceedings of the 2015 IEEE 23rd International Conference on Program Comprehension

  M. Pavlovic, M. Radulovic, A. Ramirez, and P. Radojkovic