7.1 Congresos

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    "HiPEAC Paper Award",  VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing (HPCA). Osman Sabri Unsal y Adrián Cristal, noviembre 2023.
    “Adaptable Register File Organization for Vector Processors”. Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis A. Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal and Adrián Cristal. En el 28th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2022, pp 786-799
    Adaptable Register File Organization for Vector Processors.Veljko M. Milutinovic, Erfan Sadeqi Azer, Kristy Yoshimoto, Gerhard Klimeck, Miljan Djordjevic, Milos Kotlar, Miroslav Bojovic, Bozidar Miladinovic, Nenad Korolija, Stevan Stankovic, Nenad Filipovic, Zoran Babovic, Miroslav Kosanic, Akira Tsuda, Mateo Valero, Massimo De Santo, Erich J. Neuhold, Jelena Skorucak, Laura Dipietro, Ivan Ratkovic.
    The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing”, Geo Physics, Complex Mathematics, and Information Processing.Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis A. Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal, Adrián Cristal. Adaptable Register File Organization for Vector Processors.  CoRR abs/2111.05301 (2021)
    "PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy", 27th International European Conference on Parallel and Distributed Computing (Euro-Par), to be published at the end of 2021. Vladimir Dimić, Miquel Moretó, Marc Casas and Mateo Valero.
    “VIA: A Smart Scratchpad for Vector Units With Application to Sparse Matrix Computations”” presented in the 27th IEEE International Symposium on High-Performance Computer Architecture, Seoul 2021 HPCA2021, Feb-Mar 2021. J.Pavon, I. Vargas, A. Barredo, J. Marimon, M. Moreto, F. Moll, O. Unsal, M. Valero, A. Cristal.

     

    "Runtime-Guided ECC Protection Using Online Estimation of Memory Vulnerability"

    (pap393s4), en The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC20).

    "An Academic RISC-V Silicon Implementation Based on Open-Source Components"35th Conference on Design of Circuits and Integrated Systems (DCIS), Segovia (Spain)
    Noviembre 18 - 20 2020
    J. Abella, G. Cabo, F J. Cazorla, A. Cristal, M. Doblas, R. Figueras, A. Gonzalez, C. Hernandez,
    C.Hernandez, L. Kosmidis, V. Kostalabros, R. Langarita, N. Leyva, G. Lopez-Paradis, J. Marimon,
    R. Martinez, J. Mendoza, F. Moll, M. Moreto, J. Pavon, C. Ramirez, M. A. Ramirez, C. Rojas, A. Ruiz,
    A. Rubio, N. Sonmez, V. Soria, L.Teres, O. Unsal, M. Valero, I. Vargas, L.Villa

    Improving accuracy and speeding up Document Image Classification through parallel systems
    Paper in ICCS 2020. J.Ferrando, JL. Domínguez, J.Torres, R. García, D. García, D. Garrido, J. Cortada and M. Valero
    "Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions"in the 26th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2020.
    A.Barredo, JM. Cebrian, M. Moreto, M. Casas, and M. Valero

    RICH: Implementing Reductions in the Cache Hierarchy, ICS 2020 V. Dimić, M.Moretó, M. Casas, J. Ciesko and M.

    POSTER: An Optimized Predication Execution for SIMD Extensions. PACT 2019: 479-480. 23-26 Sept. 2019. A. Barredo, JM. Cebrian, M. Moretó, M. Casas, M. Valero

    A Vulnerability Factor for ECC-protected Memory. IOLTS 2019: 176-181. 1-3 July 2019 L. Jaulmes, M. Moretó, M. Valero, M. Casas

    Optimizing Computation-Communication Overlap in Asynchronous task-Based ProgramsACM, International Conference on Supercomputing (ICS), Phoenix, USA, June 2019.

    E. Castillo, N. Jain, M. Casas, M. Moreto, M. Schulz, R. Beivide, M. Valero, A. Bhatele.

    Optimizing computation-communication overlap in asynchronous task-based programs: posterProceedings of the 24th Symposium on Principles and Practice of Parallel Programming.
    E. Castillo, N. Jain, M. Casas, M. Moreto, M. Schulz, R. Beivide, M. Valero, A. Bhatele

    Power Efficient Job Scheduling by Predicting the Impact of Processor Manufacturing VariabilityACM, International Conference on Supercomputing (ICS), Phoenix, USA, June 2019.
    D. Chasapis, M. Casas, M. Moretó, M. Schultz, B. Rountree, M. Valero

    Memory Vulnerability: A Case for Delaying Error Reporting12th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MultiProg), 2019. MP-19.
    L. Jaulmes, M. Moreto, M. Casas and M. Valero

    Optimizing computation-communication overlap in asynchronous task-based programs: posterPPoPP 2019, pp. 415-416, Washington DC, USA. [PPoPP'19]
    E. Castillo, N. Jain, M. Casas, M. Moreto, M. Schulz, R. Beivide, M. Valero, A. Bhatele.

    Network and Parallel Computing: 15th IFIP WG 103 International Conference, NPC 2018, Muroran, Japan, Proceedings. November 29–December 1, 2018.
    Volume 11276. F. Zhang, J. Zhai, M. Snir, H. Jin, H. Kasahara, M. Valero.

    Runtime-Assisted Cache Coherence Deactivation in Task Parallel ProgramsInternational Conference for High Performance Computing, Networking, Storage and Analysis (SC), Dallas, USA, Nov 2018.
    P. Caheny, Ll. Alvarez, M. Valero, M. Moretó, and M. Casas.

    Stencil Codes on a Vector Length Agnostic ArchitectureInternational Conference on Parallel Architectures and Compilation Techniques (PACT), Limassol, Cyprus, Nov 2018.
    A. Armejach, H. Caminal, J. M. Cebrian, R. Gonzalez-Arbequilla, C. Adeniyi-Jones, M. Valero, M. Casas, and M. Moretó.

    Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation DependenciesPresentado en ICS’18 Conference. June 2018.

    I. Sánchez, M. Casas, M. Moreto and M. Valero.

    Runtime-Guided Management of Stacked DRAM Memories in Task Parallel ProgramPresentado en ICS’18 Conference. June 2018.
    L. Alvarez, M. Casas, M. Moreto and M. Valero.

    Graph partitioning applied to DAG scheduling to reduce NUMA effectsPresentado en el 23o Simposio ACM SIGPLAN "on Principles and Practice of Parallel Programming". PPoPP’18. Febrero 2018.

    Architectural Support for Task Dependence Management with Flexible Software SchedulingPresentado en HPCA Febrero 2018 en Viena.
    E. Castillo, L. Alvarez, M. Moreto, M. Casas, R. Beivide, E. J.L Bosque y M. Valero.

    A machine learning approach for perfomance prediction and heterogeneous CPU schedulingPresentado en el Simposio Internacional de "Computer Architecture and High Perfomance Computing" (SBAC-PAD), Octubre 2017.
    D. Nemirovsky, T. Arkose, N. Markovic, O. Unsal, A. Cristal y M. Valero.

    A Deep learning mappers (DLM) for Heterogenous SchedulingPresentado en  la Conferencia Latino Americana de High Perfomance Computing (CARLA), septiembre 2017, pendiente de ser publicado en Cluster Computing: Special Issue Carla 2017.
    D. Nemirovsky, T. Arkose, N. Markovic, O. Unsal, A. Cristal y M. Valero.

    iQ: un marco  de simulación basado en colas eficientes y flexibles MASCOTS 201725th IEEE International Symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems Banff, AB, Canada September 20-22, 2017
    D. Roca, D. Nemirovsky, M. Nemirovsky, M. Casas, M. Moreto and M. Valero

  • Filtración de la llama y localización perimetral de los incendios forestales mediante imágenes térmicas aéreasSPIE 10214-Thermosense: Aplicaciones térmicas de infrarrojos. Volumen 10214Lisboa,Portugal; June 2017; M.M Valero, S. Verstockt, O. Rios, E. Pastor, F. Vandecasteele and E. Planas.
  • Runtime Aware Architectures. Simposio Internacional  de procesamiento paralelo y distribuido 2017 Orlando, US, June 2017.
  • Virtualización de funciones Fog: Una solución flexible para aplicaciones IoT Fog and Mobile Edge Computing (FMEC), 2017 Second International Conference. May, 2017
    D. Roca, J.V. Quiroga, M. Valero and M. Nemirovsky.
  • Runtime Aware Architectures. ACM Computación de FronterasSiena, Italia, May 15-17, 2017
  • Comunicación directa de Interprocesos (dIPC): Reutilizando la Arquitectura de CODOM para Acelerar el IPC EuroSys 2017Belgrade, Serbia, Abril 23-26, 2017
    Ll. Vilanova, M. Jordá, N. Navarro, Y. Etsion and M. Valero
  • Hardware de gestión de dependencia de tareas de propósito general para modelos de programación de flujo de datos basados en tareas IPDPS31st IEEE Simposium Internacional de procesamiento paralelo y distribuido. Orlando, Florida, USA. Mayo 29- Junio 2, 2017
    X. Tan, J. Bosch, M. Vidal, C. Alvarez-Martinez, D. Jimenez-Gonzalez, E. Ayguade and M. Valero
  • FlexVC: Gestión flexible de los canales virtuales en redes de bajo diámetro IPDPS31st IEEE Simposium Internacional de procesamiento paralelo y distribuido. Premio al mejor artículo. Orlando, Florida, USA. Mayo 29- Junio 2, 2017
    P. Fuentes, E. Vallejo, R. Beivide, C. Minkenberg and M. Valero
  • Reduciendo el tráfico de coherencia de caché con caché de directorios jerarárquicos y organización de NUMA-Aware RuntimePACT, The 25th. Conferencia de las Arquitecturas Paralelas y Técnicas de Compilación. Haifa, Israel, Septiembre 11-15, 2016. IEEE-ACM Conferencia de Supercomputación. Salt Lake, Utah, USA. Nov. 14-17th, 2016 P. Caheny, M. Casas, M. Moreto, E. Ayguade, J. Labarta and M. Valero
  • El prototipo Mont-Blanc: Un acercamiento alternativo a los sistemas HPC SC 2016. IEEE-ACM Conferencia de Supercomputación. Salt Lake, Utah, USA. Nov. 14-17, 2016 P. Mantovani et al
  • MUSA: Una infraestructura de simulación a varios niveles para las máquines de futuro generación de HPC SC 2016 T. Grass, M. Casas, M. Moreto, C. Allende, E. Ayguade, A. Armejach, J. Labarta and M. Valero
  • Un diseño de baja potencia totalmente parametrizable de Vector multiplicado fusionando usando técnicas activas de Clock-GatingISLPED Conferencia. Simposium internacional de Electrónica de baja potencia y Diseño. San Francisco, USA August 8-10, 2016 I. Ratkovic, A. Cristal, O. Palomar, M. Stanic, O. Unsal and M. Valero
  • Futuras extensiones de multiprocesadores vectoriales para la agregación de información ISCA, IEEE-ACM Conferencia Internacional de Arquitectura de Computadores. Seoul, Korea. Junio 18-22, 2016 T. Hayes, O. Palomar, O. Unsal, A. Cristal and M. Valero
  • Hacia los procesadores vectoriales incorporados de baja potenciaCF-16, The ACm Conferencia de Computadores en Frontera. Como, Italia, Mayo 16-18, 2016 M. Stanic, O. Palomar, T. Hayes, I. Ratkovic, O. Unsal, A. Cristal and M. Valero
  • CATA: Aceleración crítica consciente de la tarea para procesadores con múltipes núcleosIPDPS. 30th IEEE Simposio Internacional en Procesamiento Paralelo y distribuido. Chicago, USA, Mayo 23-27. 2016 E. Castillo, M. Moreto, M. Casas, Ll. Alvarez, E. Vallejo, K. Chronaki, R. Badia, J. L. Bosque, R. Beivide, E. Ayguade, J. Labarta and M. Valero
  • Runtime-guided mitigation of manufacturing variability in power-constrained multisocket NUMA nodes. Conferencia Internacional de Supercomputación (ICS), 2016 D. Chasapis, M. Casas, M. Moretó, M. Schulz, E. Ayguadé, J. Labarta, and M. Valero
  • Manejo a tiempo de la ejecución de memorias de Scratchpad en arquitecturas de múltiples núcleosPACT, The IEEE-ACM, 24 Conferencia Internacional en Arquitecturas paralelas y técnicas de compilación. San Francisco, USA, Octubre 18-21, 2015 Ll. Alvarez, M. Moreto, M. Casas, E. Castillo, X. Martorell, J. Labarta, E. Ayguade and M. Valero
  • Determinismo a nivel de Biblioteca estándar en aplicaciones basadas en la memoria transaccionalLa 12a IFIP Conferencia Internacional en Computación paralela y redes (NPC-2015), Septiembre 2015 V. Smiljkovic, O. Unsal, A. Cristal and M. Valero
  • VSR Sort: un nuevo Algoritmo de clasificación vectorizado y extensiones de arquitectura para multiprocesadores del futuroEn el 21 IEEE Simposio Internacional en Arquitectura de Computadores de Alto Rendimiento (HPCA2015), Febrero 2015 T. Hayes, O. Palomar, O. Unsal, A. Cristal and Valero
  • Acelerando consultas de decisión completas mediante la tecnología de síntesis de Alto nivelEn el 23o ACM/SIGDA Simposio Internacional de Matrices de puertas programables en campo (FPGA2015), Febrero 2015 G. Malazgirt, N. Sonmez, A. Yurdakul, O. Unsal and A. Cristal
  • Gestión a tiempo de la ejecución de jerarquías de memoria híbrida en arquitecturas de múltiples núcleos.Conferencia Internacional en Arquitecturas Paralelas y Técnicas de Compilación (PACT), 2015 L. Alvarez, M. Moreto, M. Casas, E. Castillo, X. Martorell, J. Labarta, E. Ayguade, and M. Valero
  • Explotación de asincronía a partir de la recuperación exacta hacia adelante debido a solvers iterativos. Conferencia Internacional en Computación de Alto Rendimiento, Redes, Almacenamiento y Análisis (SC). Nominado al mejor premio, 2015 L. Jaulmes, M. Casas, M. Moreto, E. Ayguade, J. Labarta, and M. Valero
  • Despliegue de la chispa y evaluación del rendimiento del Supercomputador MareNostrumBig Data. Octubre 29-01 Noviembre, 2015 R. Tous, A. Gounaris, C. Tripiana, J. Torres, S. Girona, E. Ayguadé, J. Labarta, Y. Becerra, D. Carrera and M. Valero
  • Programador basado en hardware de rendimiento y eficiencia para Simétrico/Asimétrico CMPs SBAC-PAD 2015. Simposio Internacional de Aquitecturas de Computadores y de Computación de Alto Rendimiento. Santa Catarina, Brasil, Octubre, 18-21, 2015 N. Markovic, D. Nemirovsky, A. Cristal, O. Unsal and M. Valero
  • Injustica en Redes de Libélulas bajo Patrones de Tráfico RealistasChicago, IL, Septiembre, 8-11, 2015 P. Fuentes, E. Vallejo, C. Camarero, R. Beivide and M. Valero
  • Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-Core Euro-par, 21 Conferencia Europea Internacional en Computación Paralela y distribuida. Vienna, Austria, Agosto 24-28, 2015 N. Markovic, D. Nemirovsky, V. Milutinovic, O. Unsal, M. Valero and A. Cristal
  • Runtime Aware Architectures 21 Conferencia Europea Internacional en Computación Paralela y distribuida (Europar 2015), Vienna, Austria, Agosto 24-28th, 2015 M. Casas, M. Moreto, Ll. Alvarez, E. Castillo, D. Chasapis, T. Hayes, L. Jaulmes, O. Palomar, O. Unsal, A. Cristal, E. Ayguade, J. Labarta and M. Valero
  • Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-core EURO-PAR 2015 Procesamiento Paralelo 2015 9233 ():122-134 N. Markovic , D. Nemirovsky, V. Milutinovic, O. Unsal, M. Valero and A. Cristal
  • Procesadores ligeros reconfigurables Procedimientos en la Conferencia Internacional de Sistemas de Computadores Embebidos: Arquitecturas, Modelaje y Simulación (SAMOS XV), Samos, Grecia, Julio 20-23, 2015 M. Duric, M. Stanic, I. Ratkovic, O. Palomar, O. Unsal, A. Cristal, M. Valero and A. Smith
  • Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors Procedimientos de IEEE Simposium Anual de Sociedad de Computadores de VLSI (ISVLSI 2015), Montpellier, Francia, Julio 8-10 2015 I. Ratkovic, O. Palomar, M. Stanic, D. Pesic, M. Djuric, O. Unsal, A. Cristal and M. Valero
  • Coherence Protocol for Transparent Management of Scratchpad Memories in Shared Memory Mnaycore Architectures IEEE-ACM ISCA, Conferencia Internacional en Arquitectura de Computadores. Portland, Oregon, USA. Junio 13-17, 2015 Ll. Alvarez, L. Vilanova, M. Moretó, M. Casa, M. González, X. Martorell, N. Navarro, E. Ayguadé and M. Valero
  • Criticality-Aware Dyanamic Task Scgedulling for Heterogeneous Architectures IEEE-ACM, ICS, Conferencia Internacional de Supercomputación. New Port Beach, California, USA. Junio 8-11, 2015 K. Chronaki, A. Rico, R. M. Badía, E. Ayguadé, J. Labarta and M. Valero
  • Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7 ADAPT 2015. The 5th International Workshop on Adaptive Self-tunig Computing Systems”. Amsterdan, Países Bajos, Enero. 21th, 2015 D. Prat, C. Ortega, M. Casas, M. Moreto and M. Valero
  • Contention-based Non-minimal Adaptive Routing in High-radix Networks IPDPS 2015. IEEE, International Parallel & Distributed Processing Symposium. Hyderabad, India, Mayo 25-29, 2015 P. Fuentes, E. Vallejo, M. García, J.R. Palacio, G. Rodríguez, C. Minkerberg and M. Valero
  • A Novel Vectorised Sorting Algorithm and Architecture Extensions for Future Microprocessors HPCA 2015. IEEE Symposium on High Performance Computer Architecture. San Francisco Bay Area, California, USA, Febrero 7-11, 2015 T. Hayes, O. Palomar, O. Unsal, A. Cristal and M. Valero
  • Aumentando la eficiencia de los sistemas con múltiples núcleas a través del movimiento inteligente del ancho de banda HPCA 2015. IEEE Simposio en Aruitecturas de Computador de Alto Rendimiento. San Francisco Bay Area, California, USA, Febrero 7-11, 2015 V. Jiménez, A. Buyuktosunoglu, P. Bose, F. P. O´Conell, F. J. Cazorla and M. Valero
  • AMMC: Controlador avanzado de memoria multi-núcleoICFPT 2014. Conferencia Internacional de Tecnología de campo programable. Shanghai, China, Diciembre 10-12, pp. 292-295, 2014 T. Hussain, O. Palomar, O. Unsal, A. Cristal, E. Ayguadé, M. Valero and S.A. Gursal
  • Dynamic-Vector Execution on a General Purpose EDGE Chip Multiprocessor Procedimientos de la Conferencia Internacional de Sistemas de Computadores incrustados: Arquitecturas, Modelaje y Simulación (SAMOS XIV), Julio 2014 M. Duric, O. Palomar, A. Smith, M. Stanic, O. Unsal, A. Cristal, M. Valero, D. Burger and A. Veidenbaum
  • Memory Controller for Vector Processor Controlador de memoria para procesador de vectores25th IEEE Conferencia Internacional de sistemas específicos aplicados: Arquitecturas y Procesadores (SAP 2014), Junio 2014 T. Hussain, O. Palomar, O. Unsal, A. Cristal, E. Ayguade and M. Valero
  • APMC: Patrón avanzado basado en el Controlador de memoria 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2014), Febrero 2014 T. Hussain, O. Palomar, O. Unsal, A. Cristal, E. Ayguadé, M. Valero and S. Rethinagiri
  • Profile-Guided Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions Proceedings of the 9th International Conference on High-Performance and Embedded Architectures and Compilation (HiPEAC'2014), Also appears on the ACM Transactions on Architecture and Code Optimization (TACO), Enero 2014 S. Stipic, V. Smiljkovic, O. Unsal, A. Cristal and M. Valero
  • PAMS: Pattern Aware Memory System for Embedded Systems ReConFig 2014. International Conference on ReConFifurable Computing and FPGAs. Cancun, México, Diciembre, 8-10, pp. 1-7, 2014 T. Hussain, N. Sonmez, O. Palomar, O. Unsal, A. Cristal, E. Ayguadé, M. Valero and S.A. Gursal
  • Characterizing the Communications Demands of the Graph500 Benchmark on a Commodity Cluster BDC 2014. IEEE/ACM International Conference on Big Data Computing. Poster Session. London, GB, Diciembre 8-9th, 2014 P. Fuentes, J. L. Bosque, J.R. Beivide, G. Rodríguez, C. Minkerberg and M. Valero
  • DeTrans: Ejecución paralela y determinista de Transacciones SBAC-PAD. 26th Simposio Internacional de Arquitectura de Computadores y Computación de Alto Rendimiento. Octubre 22-24, pp. 152-159, 2014. University Pierre et Marie Curie, Paris, France V. Smiljkovic, S. Stipic, C. Fetzer, O. Unsal, A. Cristal and M. Valero
  • MAPC. Memory Access Pattern based Controller FPL 2104. International Conference on Field Programmable Logic and Applications. Munich, Alemania. Pp. 1-4, Sept. 2-4, 2014 T. Hussain, O. Palomar, O. Unsal, A. Cristal, E. Ayguadé and M. Valero
  • DReAM: Per-Task DRAM Energy Metering in Multicore Systems Euro-Par 2014. International conference on Parallel Processing. Porto, Portugal. Agosto 25-29, 2014. pp. 111-123 Q. Liu, M. Moreto, J. Abella, F. J. Cazorla and M. Valero
  • Evaluation of Vectorization Potential of Graph500 on Intels Xeon Phi HPCS-2014. International Conference on High Performance Computing&Simulation. Bologna, Italia, Julio 21-25, 2014, pp 47-54 M. Stanic, A. Cristal, O. Palomar, I. Ratkovic, O. Unsal, M. Duric and M. Valero
  • Advanced Irregular Applications througput Data Aggregation and Software Multithreading IPDPS, 2014, pp.1126-1135 A. Morari, A. Tumeu, D. G. Chavarria-Miranda, O. Vila and M. Valero
  • Advanced Pattern based Memory Controller for FPGA based HPC Applications HPCS-2014. International Conference on High Performance Computing& Simulation. Bologna, Italia, Julio 21-25, 2014, pp.287-294 T. Hussain, O. Palomar, A. Cristal, O. Unsal, E. Ayguadé and M. Valero
  • Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders ISVLSI-2014. IEEE Computer Society Annual Symposium on VLSI. Tampa, Florida, USA. Julio 9-11, 2014, pp.118-123. M. Duric, O. Palomar, M. Stanic, A. Smith, O. Unsal, A. Cristal, M. Valero, D. Burger and A. Veidenbaum.
  • “Dynamic-Vector Execution on a General Purpose EDGE Chip Multiprocessor”. SAMOS 2014. International Conference on Embedded Computer Systems: Architectures, MOdelling and Simulation. Samos Island, Grecia, Julio 14-17, 2004, pp.18-25 I. Ratkovic, O. Palomar, M. Stanic, A. Cristal, O. Unsal and M. Valero
  • PVMC: Programmable Vector Memory Controller ASAP-2014, IEEE 25th. International Conference on Application-Specific Systems, Architectures and Processors. Zurich, Suiza, Junio, 18-20, 2014, pp.240-247 T. Hussain, O. Palomar, A. Cristal, O. Unsal, E. Ayguadé and M. Valero
  • Enabling Preemptive Multiprogramming on GPUs ISCA, IEEE-ACM, Simposio Internacional  de Arquitectura de Computadores. Minneapolis, Minnesota, USA. Junio, 14-18, 2014, pp.193-204 I. Tanasic, I. Gelado, J. Cabezas, A. Ramirez, N. Navarro and M. Valero
  • CODOMs: Protecting Software with Code-centric Memory Domains ISCA, IEEE-ACM, Simposio Internacional de Arquitectura de Computadores. Minneapolis, Minnesota, USA. Junio, 14-18, 2014, pp-469-480 L. Vilanova, M. B. Yehuda, N. Navarro, Y. Etsion and M. Valero
  • Exploración automática de paralelismo potencial en aplicaciones secuencialesISC, Leipzig, Alemania, Junio, 23-25, 2014, pp. 156-161 V. Subotic, E. Ayguadé, J. Labarta and M. Valero
  • VALib  y SimpleVector: Herramientas para una investigación inicial rápida en arquitectura de Vectores Computación de Fronteras 2014. Cagliari, Italia. Mayo 20-22th, 2014 M. Stanic, A. Cristal, O. Palomar, I. Ratkovic and M. Valero
  • Fusión dinámica de transaccionesComputación de Fronteras 2014. Cagliari, Italia. Mayo 20-22th, 2014, pp.18:1-18:10 S. Stipic, V. Karakostas, V. Smiljkvic, A. Cristal, O. Unsal and M. Valero
  • APMC: Patrón avanzado basado en el controlador de memoria FPGA 2014: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays”. Moterrey, California, USA. Feb. 26-28, 2014, pp.252 T. Hussain, O. Palomar, A. Cristal, O. Unsal, E. Ayguadé, M. Valero and S. Kumar
  • Stand-alone Memory Controller for Graphics System ARC 2014, ACM International Symposium on Applied Reconfigurable Computing. Vilamoura, Algarve, Portugal. Abril, 14-16, 2014, pp. 108-120 T. Hussain, O. Palomar, A. Cristal, O. Unsal, E. Ayguadé and M. Valero
  • Scaling Irregular Applications Through Data Aggregation and Software Multithreading IPDPS, the 28th. IEEE International Parallel & Distributed Processing Symposium. Phoenix, Arizona, Mayo 19-23, 2014 A. Morari, A. Tumeo, D. Chavarria, O. Villa and M. Valero
  • EVX: Vector Execution on Low Power EDGE Cores DATE, Design, Automation & Test in Europe. Dresden, Alemania. Marzo 24-28, 2014, pp.1-4 M. Duric, O. Palomar, A. Smith, O. Unsal, A. Cristal, M. Valero and D. Burger
  • Authors retrospective for Software Trace Cache. Seleccionado como uno de los mejores artículos de los últimos 25 años. ICS 25 Aniversario, pp.45-47, 2014 A. Ramirez, A. Falcón, O. J. Santana and M. Valero
  • Supercomputing with commodity CPUs: Are Mobile SoCs ready for HPC? SC-2013, the IEEE and ACM Supercomputing Conference. Best Paper Award. Denver, Colorado, USA, Nov.17-22, 2013, pp. 40-47 N. Rajovic, P. M. Carpenter, I. Gelado, N. Puzovic, A. Ramírez and M. Valero
  • GMT: Enabling Easy Development and Efficient Execution of Irregular Applications on Commodity Clusters2 Poster. SC-2013, the IEEE and ACM Supercomputing Conference. Denver, Colorado, USA, Nov.17-22, 2013, pp. 2242-2245 A. Morari, A. Tomeu and M. Valero
  • HPC System software for Regular and Irregular Paarllel Applications Poster presentation during the IPDPS 2013 PhD Forum. IEEE International Parallel and Distributed Processing Symposium. Phoenix, Arizona, Mayo 19-23, 2013 A. Morari and M. Valero
  • APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation DAC 2013. Austin, Texas, USA, 84 B. Maric, J. Abella and M. Valero
  • HPCS 2013 panel: The era of exascale sciences: Challenges, needs and requirements HPCS 2013 F. Cappello, W. Gentzsch, M. Valero and M. Nygård
  • Efficient Cache Architecture for Reliable Hybrid Voltage Operation Using EDC Codes DATE 2013, pp. 917-920 B. Maric, J. Abella and M. Valero
  • EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory ICCS 2013: 270-279 S. Tomic, E. Akpinar, A. Cristal, O. Unsal and M. Valero
  • On the selection of adder unit in energy efficient vector processing ISQED 2013, pp. 143-150 I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal and M. Valero
  • Identifying Critical Code Sections in Dataflow Programming Models Euromicro Conference on Parallel, Distributed and Network-Based Processing. PDP 2013. Belfast, Feb. 27- Marzo 01, pp. 29-37 V. Subotic, J. C. Sancho, J. Labarta and M. Valero
  • Killer-mobiles - The Way Towards Energy Efficient High Performance Computers? PECCS 2013 M. Valero
  • Efficient Routing Mechanisms for Dragonfly Networks ICPP-2013, International Conference on Parallel Processing. Lyon, Francia, Octubre 1-4, 2013, pp.582-592 M. García, E. Vallejo, J. R. Beivide, M. Odriozola and M. Valero
  • Efficient Dragonfly Networks with Simple Congestion Management HOTI, the IEEE Symposium on High Performance Interconnects. Santa Clara, California, USA, Agosto 24-26th, 2013, pp.55-62 M. García, E. Vallejo, J. R. Beivide, M. Valero and G. Rodríguez
  • The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices DSD, Euromicro Conference on Digital System design. Santander, España, Septiembre 4-6th, 2013, pp. 272-279 M. Solinas1, R. M. Badia2, F. Bodin3, A. Cohen4, P. Evripidou5, P. Faraboschi6, B. Fechner7, G. R. Gao8, A. Garbade7, S. Girbal9, D. Goodman10, S. Koliai8, F. Li4, M. Luján10, L. Morin3, A. Mendelson11, N. Navarro2, A. Pop4, P. Trancoso5, T. Ungerer7, M. Valero2, S. Weis7, I. Watson10, S. Zuckermann8 and R. Giorgi1
  • Killer-mobiles - The Way Towards Energy Efficient High Performance Computers? ACSD, 2013 M. Valero
  • Trace Filetring of Multithreaded Applications for CMP Memory Simulation ISPASS. IEEE International Symposium on Performance Analysis of Systems and Software. Austin, USA, Abril 21-23, 2013, pp.134-135 A. Rico, A. Ramirez and M. Valero
  • On the Selection of Adder Unit in Energy Efficient Vector Processing ISQED Symposium. Santa Clara, USA, Marzo 4-6, 2013, pp.143-150 I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal and M. Valero
  • TM-dietlibc: A TM-aware Real-world System Library IEEE IPDPS 2013, The 27th IEEE International Parallel & Distributed Processing Symposium. Boston, USA, Mayo 20-24, 2013, pp. 1266-1274 V. Smiljkovic, M. Nowack, N. Miletic, T. Harris, O. Unsal, A. Cristal and M. Valero
  • Fair CPU Accounting in CMP+SMT Processors HiPEAC, 8th International Conference on High Performance and Embedded Architectures and Compilers. Berlin, Alemania. Enero 21-23, 2013 C. Luque, M. Moreto, F. J. Cazorla and M. Valero
  • Global Misrouting Policies in Two-level Hierarchical Networks INA-OCMC Workshop, Interconnection Network Architectures: On-chip, Multichip. To be colocated with HiPEAC, 8th International Conference on High Performance and Embedded Architectures and Compilers. Berlin, Alemania. Enero 21-23, 2013 M. García, E. Vallejo, R. Beiivide, C. Camarero, M. Valero, G. Martínez and J. Labarta
  • Vector Extensions for Decision Support DBMS Aceleration Micro-45. The IEEE and ACM International Symposium on Microarchitecture. Vancouver, Canada. Dic. 1-5, pp. 166-176, 2012 T. Hayes, O. Palomar, O. Unsal, A. Cristal and M. Valero
  • Improving Cache Management Policies Using Dynamic Reuse Distances Micro-45.The IEEE and ACM International Symposium on Microarchitecture. Vancouver, Canada. Dic. 1-5, pp. 389-400, 2012 N. Duong, D. Zhao, T. Kim, R. Cammarota, A. Veidenbaum and M. Valero
  • Efficient Sorting on the Tilera Manycore Architecture SBAC-PAD. 24th International Symposium on Computer Architecture and High Performance Computing. Nueva York, USA, Octubre 24-26, 2012 A. Morari, A. Tumeo, S. Secchi, O. Villa and M. Valero
  • The Network Adapter: The Missing Link between MPI Applications and Network Performance SBAC-PAD. 24th International Symposium on Computer Architecture and High Performance Computing. Nueva York, USA, Octubre 24-26, pp. 1-8, 2012 G. Rodriguez, C. Minkenberg, R. P. Luijten, R. Beivide, P. Geoffray, J. Labarta, M. Valero and S. Poole
  • On-the-Fly Adoptive Routing in High-Radix Hierarchical Network Best paper Award. ICPP. IEEE International Conference on Parallel Processing. Pittsburgh, USA. Septiember 11-13, pp. 279-288, 2012 M. García, E. Vallejo, R. Beivide, M. Odriozola, C. Camareno, M. Valero, G. Rodríguez, J. Labarta and C. Minikemberg
  • Combining PGAS Programming Models with Lighweight Threading on Many-core Architectures Poster. SC2012, ACM, Supercomputing Conference. Salt Lake, pp. 171-178, Nov. 2012 A. Morari, A. Tumeo, O. Villa and M. Valero
  • Enhencing the Performance of Assisted Execution Runtime Systems Through Hardware/Software Techniques”. ICS, ACM INternational Conference on Supercomputing. Venice, Italia, Junio 25-29, pp. 153-162, 2012 G. Kestor, R. Gioiosa, O. Unsal, A. Cristal and M. Valero
  • ADAM: An efficient data management mechanism for hybrid high and ultra-low voltage operation caches GLSVLSI, ACM Symposium on VLSI. Great Lakes, pp. 245-250, 2012 B. Maric, J. Abella, F.J. Cazorla and M. Valero
  • On the simulation of large-scale architectures using multiple application abstraction levels ACM Trans. Archit. Code Optim. 8, 4, Article 36 (Enero 2012) A. Rico, F. Cabarcas, C. Villavieja, M. Pavlovic, A. Vega, Y. Etsion, A. Ramírez, and M. Valero
  • Evaluating the Impact of TLB Misses on Future HPC Systems Best Paper Award. IPDPS, IEEE International Parallel and Distributed Processing Symposium. Shanghai, China, Mayo 21-25, pp. 1010-1021, 2012 A. Morari, R. Giogiosa, R. Wisniewsky, B. Rosenburg, T. Inglett and M. Valero
  • Optimal Task Assignment in Multithreaded Processors: A Statistical Approach ASPLOS, ACM, International Conference on Architectural Support for Programming Languages and Operating Systems. Londres, GB, Marzo 3-7, pp. 235-248, 2012 P. Radojkovic, V. Cacarevic, M. Moreto, J. Verdú, A. Pajuelo, F. J. Cazorla, M. Nemirovsky and M. Valero
  • Hardware/Software Techniques for Assisted Execution Runtime Systems RESoLVE, Workshop on Runtime Environments, Systems, Layering and Virtualized Environments. Colocated with ASPLOS, ACM, International Conference on Architectural Support for Programming Languages and Operating Systems. London, UK, Marzo 3-7, 2012 G. Kestor, R. Giogiosa, O. Unsal, A. Cristal and M. Valero
  • TagTM: Accelerating STMs with Hardware Tags for Fast Meta-Data Access DATE, Design, Automation and Test in Europe. Dresden, Germany, 12-16, pp. 39-44, Marzo, 2011 S. Stipic, F. Zyulkyarov, S. Tomic, O. Unsal, A. Cristal and M. Valero
  • Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime testing SBAC-PAD, 23th. International Symposium on Computer Architecture and High Performance Computing. Vitória, Espirito Santo, Brazil, pp. 80-87, Octubre 2011 S. Tomic, A. Cristal, O. Unsal and M. Valero
  • STM2: A paralle STM for High Performance Simultaneous Multithreading Systems PACT 2011. IEEE and ACM International Conference on Parallel Architectures and Compilation techniques. Galveston Island, Texas, USA, Octubre 10-14, pp. 221-231, 2011 G. Kestor, R. Gioiosa, T. Harris, O. Unsal, A. Cristal, I. Hur and M. Valero
  • FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware To appear in 2011 Workshop on Wild and Sane Ideas in Speculation and Transactions (WANDS11) held in conjunction with the 20th International Conference on Parallel Architectures and Compilation Techniques (PACT’2011), Octubre 2011 G. Yalcin, O. Unsal, A. Cristal and M. Valero
  • Using a Reconfigurable L1 data cache for Efficient Version management in Hardware Transactional Memory PACT 2011. IEEE and ACM International Conference on Parallel Architectures and Compilation techniques. Galveston Island, Texas, USA, Octubre 10-14, pp. 361-371, 2011 A. Armejach, A. Seyedi. R. Titos, I. Hur, O. Unsal, A. Cristal and M. Valero
  • FIMSIM: A Fault Injection Infrastructure for Microarchitectural Simulators ICCD, 29th International Conference on Computer Design, pp. 431-432, Octubre 2011 G. Yalcin, O. Unsal, A. Cristal and M. Valero
  • SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory Poster Session. PACT 2011. IEEE and ACM International Conference on Paralklel Architectures and Compilation techniques. Galveston Island, Texas, USA, Octubre 10-14, pp. 199-200, 2011 G. Yalcin, O. Unsal, A. Cristal, I. Hur and M. Valero
  • Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications Europar 2011. Bordeaux, Francia, Agosto 29- Septiembre 2, pp. 39-51, 2011 V. Subotic, J. C. Sancho, J. Labarta and M. Valero
  • An Abtraction Methodology for the Evaluation of Multi-Core Multi-Threaded Architectures MASCOTS 2011. IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems”. Singapore, Julio 25-27, pp. 478-481, 2011 R. Zilan, J. Verdu, J. García, M. Nemirovsky, R. Milito and M. Valero
  • RVC-Based Time-Predictable Faulty Caches for safety-Critical Systems IOLTS 2011. IEEE International On-line Testing Symposium. Athens, Grecia, Julio 13-15, pp. 25-30, 2011 J. Abella, E. Quiñones, F. J. Cazorla, Y. Sazeides and M. Valero
  • Object Oriented Execution Model (OOM) 2nd Workshop on New Directions in Computer Architecture (NDCA-2), held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38), Junio 2011 N. Markovic, D. Nemirovsky, O. Unsal, M. Valero and A. Cristal
  • RMS-TM: a comprehensive benchmark suite for transactional memory systems ICPE 2011: 335-346 G. Kestor, V. Karakostas, O. Unsal, A. Cristal, I. Hur and M. Valero
  • A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory Sixth ACM SIGPLAN Workshop on Transactional Computing TRANSACT, Junio 2011 Ismail Ege Akpinar, Sasa Tomic, O. Unsal, A. Cristal and M. Valero
  • Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency ACM, Great lakes Symposium on VLSI. Lausanne, Suiza, May o2-6, pp. 325-330, 2011 A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur and M. Valero
  • Hybrid Parallel Programming with MPI/StarSs PARCO 2011: 621-628 J. Labarta, V. Marjanovic, E. Ayguadé, R. M. Badia and M. Valero
  • TMbox: A Flexible and reconfigurable 16-core Hybrid Transactional Memory System FCCM 2011. The 19th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. Salt Lake City, Utah, USA, pp. 146-153, Mayo 1-3, 2011 N. Sonmez, O. Arcas, O. Pflucker, O. Unsal, A. Cristal, I. Hur, S. Singh and M. Valero
  • Hybrid High Performance low-power and ultra low energy reliable caches CF, ACM Computing Frontiers. Ischia, Italy, Mayo 3-5, 2011 B. Maric, J. Abella, F.J. Cazorla and M. Valero
  • Integrating Dataflow Abstractions into Transactional Memory 2011 Workhop on Systems for Future Multi-Core Architectures (SFMA), Abril 2011 V. Gajinov, M. Milovanovic, O. Unsal, A. Cristal, E. Ayguade and M. Valero
  • From plasma to beefarm: Design experience of an FPGA-based multicore prototype ARC 2011, 7th International Conference on Applied Reconfigurable Computing, Marzo 23-25, pp. 350-362, Belfast, UK N. Sonmez, O. Arcas, G. Sayilar, O. Unsal , A. Cristal, I. Hur, S. Singh and M. Valero
  • Linear programming Based Parallel Job Scheduling for Power Constrained Systems HPCS 2011. The IEEE, ACM and IFIP International Conference on High Performance Computing& Simulation. Instambul, Turquía, pp. 72-80, Julio 4-8. Outstanding Paper Award M. Etinski, J. Corbalán, J. Labarta and M. Valero
  • The Impact of Application’s Micro-Imbalance on the Communication-Computation Overlap PDP 2011. The 19th Euromicro International Conference on Parallel, Distributed and Network-based Computing. Chipre, Febrero 9-11, 2011, pp. 191-198 V. Subotic, J. C. Sancho, J. Labarta and M. Valero
  • Breaking the Bandwidth Wall in Chip Multiprocessors Samos 2011: International Conference on Embedded Computer Systems; Architecture, Modelling and Simulation. SAMOS 11. Samos, Grecia. Julio 18-21, pp. 255-262, 2011 A. Vega, F. Cabarcas, A. Ramírez and M. Valero
  • Trace-driven Simulation of Multithreaded Applications ISPASS, IEEE International Symposium on Performance Analysis of Systems and Software, Austin, Texas, Abril, 10-12, pp. 87-96, 2011 A. Rico, A. Durán, F. Cabarcas, Y. Etsion, A. Ramírez and M. Valero
  • A Quantitative Analysis of OS Noise IPDPS, Inteational Parallel and Distributed Processing Symposium. Anchorage, Alaska. Mayo 16-20, pp. 852-863, 2011 A. Morari, R. Giogiosa, R. Wisniewski, F. J. Cazorla and M. Valero
  • IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems IEEE Real-Time and Embedded Technology and Applications synposium. Chicago, IL, USA. Abril 11-14, pp. 280-290, 2011
  • A New Benchmark Suite for Transactional Memory 2nd Joint WOSP/SIPEW. ACM ICPE, International Conference on Performance Engineering. Karlshure, Alemania, Marzo, 14-16, 2011. Best Paper Award G. Kestor, V. Karakostas, O. Unsal, A. Cristal, I. Hur and M. Valero
  • RVC, A mechanism for Time-Analizable Real-Time Processors with Faulty Caches HiPEAC, International Conference on High Performance Embedded Architectures and Compilers. Heraklion, Crete, Grecia, Enero 24-26, pp. 97-106, 2011 J. Abella, E. Quiñones, F. J. Cazorla, Y. Sazeides and M. Valero
  • Task Superscalar: An Out-of-Order Task Pipeline Micro-43, the IEEE-ACM International Conference on Computer Architecture. Atlanta, Georgia, USA, Diciembre 4-8, 2010 Y. Etsion, F. Cabarcas, A. Rico, A. Ramírez, R. M. Badía, E. Ayguadé, J. Labarta and M. Valero
  • Architectural Support for Fair Reader-Writer Locking Micro-43, the IEEE-ACM International Conference on Microarchitecture. Atlanta, Georgia, USA, Diciembre 4-8, 2010 E. Vallejo, R. Beivide, A. Cristal, T. Harris, F. Vallejo, O. Unsal and M. Valero
  • Scalability Analysis of Progreesive Alignment on a Multicore CISIS 2010. International Conference on Computational Intelligence in Security for Information Systems. Leon, España, Noviembre 11-12, 2010 S. Izasa, F. Sánchez, G. Gaydadjiev, A. Ramírez and M. Valero
  • A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications Cluster 20101. IEEE International Conference on Cluster Computing. Heraklion, Crete, Septiembre 20-24, 2010 V. Subotic, J. Sancho, J. Labarta and M. Valero
  • Designing OS for HPC Applications Cluster 20101. IEEE International Conference on Cluster Computing. Heraklion, Crete, Septiembre 20-24, 2010 R. Giogiosa, S. A. McKee and M. Valero
  • ITCA: Inter-Task Conflict Aware CPU Accounting for CMPs Jornadas de Paralelismo. Congreso CEDI, Valencia, Septiembre 2010 C. Luque, M. Moreto, F.J. Cazorla, R. Giogiosa and M. Valero
  • BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems Proceedings of the COSTAction IC0804 on Large Scale Distributed Systems 1st Year. Jean-MarcPierson, Helmut Hlavacs (Ed.) pp. 76-79. ISBN: 978-2-917490-10-5 J. Torres, E. Ayguadé, D. Carrera, J. Guitart, V. Beltran, Y. Becerra, R. M. Badia, J. Labarta and M. Valero
  • Eficcient Runahead Threads PACT 2010. IEEE and ACM International Conference on Parallel Architectures and Compiler Techniques. Vienna, Septiembre 11-15, 2010 T. Ramírez, O. J. Santana, A. M. Pajuelo and M. Valero
  • Discovering and Understanding Performance Bottlenecks in Transactional Applications PACT 2010. IEEE and ACM International Conference on Parallel Architectures and Compiler Techniques. Vienna, Septiembre 11-15, 2010. Best Paper Award F. Zyulkyarov, S. Stipic, T. Harris, O. Unsal, A. Cristal, I. Hur and M. Valero
  • Power and Termal Characterization of Power6 System PACT, IEEE and ACM Conference on Parallel Architectures and Compilation Techniques. Vienna, Austria, Sept. 11-15, pp. 7-18, 2010 V. Jiménez, F. J. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, P. Bose and M. Valero
  • Long DNA Sequence Comparison on Multicore Architectures Europar 2010. Ischia, Italia, Agosto 31- Septiembre 3, 2010 F. Sánchez, F. Cabarcas, A. Ramírez and M. Valero
  • Optimizing Job Performance Schedulers Under a Given Power Constraint in HPC Centers IEEE, International Green Computing Conference. Chicago, Agosto 15-18, 2010 M. Etinski, J. Corbalán, J. Labarta and M. Valero
  • RMS-TM++, A New Transactiona Memory Benchmark Suite ACACES 2010, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Terrassa, Julio 14. Academia Press ISBN 978 90 382 1631 7 V. Karakostas, G. Kestor, O. Unsal, A. Cristal, I. Hur and M. Valero
  • Comparing Last-level Cache Designs for CMP Architectures IFMT, the Second International Forum on Next Generation Multicore/Manycore Technologies. Held in conjuction with ISCA, the IEEE-ACM International Symposium on Computer Architecture. Renens, Francia, Junio 19-23, 2010 A. Vega, A. Rico, F. Cabarcas, A. Ramírez and M. Valero
  • Power and Performance Aware Reconfigurable Cache for CMPs IFMT, the Second International Forum on Next Generation Multicore/Manycore Technologies. Held in conjuction with ISCA, the IEEE-ACM International Symposium on Computer Architecture. Renens, Francia, Junio 19-23, 2010 K. Kedzierski, F. J. Cazorla, R. Giogiosa, A, Buyuktosunoglu and M. Valero
  • Fault-Tolerance Using Hardware Transactional Memory PESPMA. Workshop on Parallel Execution of Sequential Programs on Multicore Architectures. Held in conjuction with ISCA, the IEEE-ACM International Symposium on Computer Architecture. Rennes, Francia, Junio 19-23, 2010 G. Yalcin, O. Unsal, I. Hur, A. Cristal and M. Valero
  • A Case for Energy-Aware Accounting in Large Scale Computing Facilities: Cost Metrics and implications for Processing Design ACLD, second Workshop on Architectural Concerns in Large Datacenters. Held in conjuction with ISCA, the IEEE-ACM International Symposium on Computer Architecture. Rennes, Francia, Junio 19-23, 2010 V. Jiménez, F. J. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, P. Bose and M. Valero
  • Overlaping Communication and Computation for using a Hybrid MPI/SMPSs Approach ICS, the ACM International Conference on Supercomputing. Tsukuba, Japón, Junio 1-4, 2010 V. Marjanovic, E. Ayguadé, J. Labarta and M. Valero
  • Simulation Environment to Study Overlaping of Communication and Computation ISPASS, the IEEE International Symposium on Performance Analysis of Systems and Software. Marzo, 28-30, Nueva York, 2010, pp.115-116 V. Subotic, J. Labarta and M. Valero
  • Task Superscalar: Using Processors as Functional Units USENIX HotPar 2010 workshop to be held at the USENIX Conference. Junio 14–15, 2010 Berkeley, USA Y. Etsion, A. Ramirez, R. Badia, E. Ayguade, J. Labarta and M. Valero
  • Transactification of a real-world system library 5th ACM SIGPLAN Workshop on Transactional Computing, TRANSACT 2010. To be held in conjunction with EuroSys 2010. Abril 13, 2010, Paris, Francia N. Miletic, V. Smiljkovic, C. Perfumo, T. Harris, A. Cristal, I. Hur, O. Unsal and M. Valero.
  • Hardware Transactional Memory with Software-Defined Conflicts 5th ACM SIGPLAN Workshop on Transactional Computing, TRANSACT 2010. To be held in conjunction with EuroSys 2010. Abril 13, 2010, Paris, Francia R. Titos-Gil, M. E. Acacio, J. M. García, T. Harris, A. Cristal, O. Unsal, I. Hur and M. Valero
  • Load Balancing Using Dynamic Cache Allocation The ACM International Conference on Computing Frontiers, CF-2010. Mayo 17-19, 2010, Bertinoro, Italia M. Moretó, F. J. Cazorla, R. Sakellariou and M. Valero
  • Adapting Cache Partitioning to Real pseudo-LRU Replacement Policies IPDPS-24, IEEE International Parallel & Distributed Processing Symposium. Atlanta, USA, Abril 19-23, 2010 K. Kedzierski, M. Moreto, F. J. Cazorla and M. Valero
  • BSLD Threshold Driven Power Management Policy for HPC Centers HPPAC2010. Workshop on High-Performance Power-Aware Computing. To be held in conjuction with the IEEE IPDPS, International Paralle&Distributed Processing Systems. April, 19, Atlanta, Georgia, 2010 M. Etinski, J. Corbalán, J. Labarta and M. Valero
  • Exploiting Inactive Rename Slots for Detecting Soft Errors In the proceedings of the 23th Conference on Architecture of Computing Systems (ARCS’10), Hannover, Alemania, Febrero 2010 M. Kayaalp, O. Ergin, O. Ünsal and M. Valero
  • Scalability Analysis of Progressive Alignement on a Multicre CISIS, International Conference on Complex, Intelligent and Software Intensive Systems. Krakow, Polonia, Febrero 15-18, 2010 S. Izasa, F. Sánchez, G. Gaydadjiev, A. Ramírez and M. Valero
  • Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems PPoPP 2010. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. Bangalore, India, Enero 9-14, 2010 P. Radojković, V. Čakarević, J. Verdú, A. Pajuelo, F. J. Cazorla, M. Nemirovsky and M. Valero
  • Overlapping Communication and Computation by Using a Hybrid MPI/SMPSs Approach Poster. PPoPP 2010. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. Bangalore, India, Enero 9-14, 2010 V. Marjanovic, E. Ayguadé, J. Labarta and M. Valero
  • Trends and Techniques for Energy Efficient Architectures VLSI-SOC, IFIP, TC-10, Madrid, Septiembre 25-29, 2010 V. Jiménez, R. Gioiosa, E. Kursun, F. J. Cazorla, C. Isci, A. Buyuktosunoglu, P. Bose and M. Valero
  • Debugging Programs that use Atomic Blocks and Transactional Memory PPoPP 2010. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. Bangalore, India, Enero 9-14, 2010 F. Zyulkyarov, T. Harris, O. Unsal, A. Cristal and M. Valero
  • Scalability of Macroblock-level Parallelism for H.264 Decoding ICPADS, the IEEE International Conference on Parallel and Distributed Systems. Shenzhen, China, Diciembre 8-11, 2009 M. Alvarez, A. Ramírez, A. Azevedo, C. Meenderinck, B. Juurlink and M. Valero.
  • Characterizing the resource-sharing levels in the UltraSPARC T2 processor Micro-2009, the IEEE-ACM International Conference on Microarchitecture. Nueva York, Diciembre 12-16, 2009 V. Cakarevic, P. Radojkovic, J. Verdu, A. Pajuelo, F. J. Cazorla, M. Nemirovsky and M. Valero
  • EazyHTM, Eager-Lazy Hardware Transactional Memory Micro-2009, the IEEE-ACM International Conference on Microarchitecture. Nueva York, Diciembre 12-16, 2009 S. Tomic, C. Perfumo, C. Kulkarni, A. Cristal, O. Unsal, T. Harris and M. Valero
  • Scalability of Macroblock-level Parallelism for H.264 Decoding ICPADS 2009. IEEE International Conference on Parallel and Distributed Systems. Shenzhen, China, Diciembre 8-11, 2009, pp. 236-243 M. Alvarez, A. Ramírez, A. Azevedo, C. Meenderinck, B. H. H. Juurling and M. Valero
  • Thread to Core Assignment in SMT On-Chip Multiprocessors SBAC-PAD- 2009. Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Sao Paulo, Brasil, Oct-28-31, 2009 C. Acosta, A. Ramírez, F. J. Cazorla and M. Valero
  • Code Semantic-Aware Efficient Runahead Threads ICPP-2009, International Conference on Parallel Processing. Vienna, Austria, Sept. 22-25, 2009 T. Ramírez, O. Santana, A. M. Pajuelo and M. Valero
  • ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs PACT, IEEE and ACM Conference on Parallel Architectures and Compilation Techniques. Raleigh, North Carolina, Septiembre 12-16, 2009 C. Luque, M. Moretó, F. J. Cazorla, R. Giogiosa, A. Buyuktosunoglu and M. Valero
  • Pseudo-LRU based Cache Partitioning Algorithms Poster Session. PACT, IEEE and ACM Conference on Parallel Architectures and Compilation Techniques. Raleigh, North Carolina, Septiembre 12-16, 2009 K. Kedzierski, M. Moreto, F. J. Cazorla and M. Valero
  • Oblivious Routing Schemes in Extended Generalized Fat Tree Networks International Workshop on High Performance Interconnects for Distributed Computing (HPI-DC), 2009, in conjuction with Cluster 2009, New Orleans, Agosto 31, 2009 G. Rodriguez, C. Minkenberg, R. Beivide, R. Luijten, J. Labarta and M. Valero
  • Direct Networks Simulation with Actual HPC Traffic ACACES 2009, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Terrassa, Julio 15. Academia Press ISBN 978 90 382 1467 2, pp281-284 M. García, G. Rodríguez, R. Beivide, J. L. Bosque, J. Labarta and M. Valero
  • Internet Traffic and the Behavior of Processing Workloads ACACES 2009, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Terrassa, Julio 15. Academia Press ISBN 978 90 382 1467 2 pp. 269-272 R. Zilan, J. Verdú, J. García, M. Nemirovsky and M. Valero
  • Multicore Architecture for Hard Real-Time Systems ACACES 2009, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Terrassa, Julio 15. Academia Press ISBN 978 90 382 1467 2 pp 199-202 M. Paolieri, E. Quiñones, F. J. Cazorla, G. Bernat and M. Valero
  • Measuring Operating System Overhead on Sun UltraSPARC T1 Processor ACACES 2009, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Terrassa, Julio 15. Academia Press ISBN 978 90 382 1467 2 pp. 187-190 P. Radojkovic. V. Cakarevic, J. Verdú, A. Pajuelo, R. Gioiosa, F. J. Cazorla, M. Nemirovsky and M. Valero
  • Software Transactional Memory Implementation ACACES 2009, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Terrassa, Julio 15. Academia Press ISBN 978 90 382 1467 2 pp. 101-103 N. Sonmez, C. Perfumo, S. Stipic, T. Harris, O. Unsal, A. Cristal and M. Valero
  • Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory Best Paper Award, 11th IEEE International Conference on High Performance Computing and Communications (HPCC-09) Junio, 2009, Seoul. S. Sanyal, S. Roy, A. Cristal, O. Unsal and M. Valero
  • Hardware Support for WCET Analysis of Hard Real-Time Multicore Systems ISCA-2009, the IEEE and ACM International Conference on Computer Architecture. Austin, USA, Junio 2009 M. Paolieri, E. Quiñones, F. J. Cazorla, G. Bernat and M. Valero
  • QuakeTM: Parallelizing a Complex Serial Application Using Transactional Memory ICS, the ACM International Conference on Supercomputing. Nueva York, Junio 2009 V. Gajinov, F. Zyulkyarov, A. Cristal, O. Unsal, E. Ayguadé, T. Harris and M. Valero
  • Exploiting Pattern- Aware Patterns in Generalized Fat Tree Networks ICS, the ACM International Conference on Supercomputing. Nueva York, Junio 2009 G. Rodríguez, M. Beivide, C. Minkenberg, J. Labarta and M.Valero
  • A European Perspectice on Supercomputing Keynote lecture. ICS, the ACM International Conference on Supercomputing. Nueva York, Junio 2009 M. Valero, J. Labarta and E. Ayguade
  • Architectural Mechanisms Leveraging the Floating Point Subsystem for Soft Error Mitigation CATARS-2, Second Workshop on Compiler and Architectural Techniques for Application Reliability and Security. In Conjunction with the 39th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2009). Estoril, Portugal, Junio 2009 G. Yalcin, O. Unsal and M. Valero
  • Taking the Heat of Transactions: Dynamic Selecction of Pessimistic Concurrency Control IPDPS. IEEE-ACM International Parallel and Distributed Processing Symposium. Rome, Mayo 2009 N. Sonmez, A. Cristal, T. Harris, O. Unsal and M. Valero
  • Power-Aware Load Balancong of Large Scale MPI Applications Workshop on “High-Performance Power-Aware Computing”. To be held in conjuction with the IEEE-ACM IPDPS, International Parallel and Distributed Processing Symposium, Rome, Mayo 2009 M. Etinski, J. Corbalan, J. Labarta, M. Valero and A. Veidenbaum
  • Clock Gate on Abort: Towards Energy-Efficient Hardware Transactional Memory Fifth IEEE Workshop on High-Performance, Power-Aware Computing (HP-PAC), in conjuction with IPDPS 2009, IEEE-ACM International Parallel and Distributed Processing Symposium, Roma, Mayo 2009 S. Sanyal, S. Roy, A. Cristal, O. Unsal and M. Valero
  • Quantitative Analysis of Sequence Alignment Applications on Multiprocessor Architectures Computing Frontieres Ischia, Italy, May 2009 F. Sánchez, A. Ramirez and M. Valero
  • Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture Cuarto Congreso Colombiano de Computación, 4CºCC, organizado por la Sociedad Colombiana de Computación S(Co)2. Universidad Autónoma de Bucaramanga, UNAB. Abril, 2009 M. Alvarez, A. Ramírez, A. Azevedo, C. Meenderinck, B. Juurlink and M. Valero
  • Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem Cuarto Congreso Colombiano de Computación, 4CCC, organizado por la Sociedad Colombiana de Computación S(Co)2. Universidad Autónoma de Bucaramanga, UNAB. Abril, 2009 F. Sánchez, A. Ramirez and M. Valero
  • Atomic Quake: Use Case of Transactional Memory in an Intearctive Multiplayer Game Server PPoPP 2009. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. Raleigh, North Carolina, Febrero 12-14, 2009 F. Zyulkyarov, V. Gajinov, O. Unsal, A. Cristal, E. Ayguade, T. Harris and M. Valero
  • Turbocharging boosted transactions or: How I Learnt to Stop Worrying and Love Longer Transactions Poster Session, 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) - Feb 2009 C. Kulkarni, O. Unsal, A. Cristal, E. Ayguade and M. Valero
  • RMS-TM: A Transactional Memory Benchmark for Recognition, Mining and Synthesis Applications 4th ACM SIGPLAN Workshop on Transactional Computing, TRANSACT 2009 - Feb 2009 G. Kestor, S. Stipic, O. Unsal, A. Cristal and M. Valero
  • Turbocharging boosted transactions or: how I learnt to stop worrying and love longer transactions PPoPP 2009. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. Raleigh, North Carolina, Febrero 12-14, 2009 C. Eishan, O. Unsal, A. Cristal, E. Ayguadé and M. Valero
  • Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study MULTIPROG 2009 - Enero 2009 N. Sonmez, A. Cristal, O. Unsal, T. Harris and M. Valero
  • Exploiting the Dependency Checking Log
  • ic of the Rename Stage for Soft Error Detection First Workshop on Design for Reliability (DFR), in conjunction with Hipeac Conference, Enero 2009 O. Ergin, G. Yalcin, O. Unsal and M. Valero
  • A Distributed Processor State Management Architecture for Large-Window Processors Micro-41, IEEE-ACM “International Symposium on Microarchitecture”. Lake Como, Italia, Novimbre 8-12, 2008 I. González, M. Galluzzi, A. Veidenbaum, M. A. Ramírez, A. Cristal and M. Valero
  • MultiLayer Processing: An Execution Model for Parallel Stateful Packet Processing ANCS08, ACM-IEEE Symposium on Architectures for Networking and Communications Systems. San Jose, California, Noviembre 6-7, 2008 J. Verdu, M. Nemirovsky and M. Valero
  • A Dynamic Scheduler for Balancing HPC Applications IEEE Supercomputing Conference, ISC. Austin, Noviembre, 2008 C. Bonetti, F. J. Cazorla, R. Gioiosa and M. Valero
  • Selection of the Register File Size and the Resource Allocation Policy on SMT Processors Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, 29 Oct- 1 Nov. 2008. IEEE Computer Society, p. 63-70, ISBN 978-0-7695-3423-7 J. Alastruey, T. Monreal, F.J. Cazorla, V. Viñals and M. Valero
  • Measuring Operating Syastem Overhead on CMT Processors IEEE SBAC-PAD, Campo Grande, Brasil, Octubre 29 a Noviembre 1, 2008 P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. J. Cazorla, R. Gioiosa, M. Nemirosvky and M. Valero
  • WormBench: A Configurable Workload for Evaluating Transactional Memory Systems MEDEA Workshop. TCPP-PhD- Forum’09 PACT, the IEEE Conference on Parallel Architectures and Compilation Techniques. Toronto, Canada, Octubre 25-29, 2008 F. Zyulkyarov, O. Unsal, A. Cristal, E. Ayguade, S. Cvijic, T. Harris and M. Valero
  • MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors ICPP, International Conference on Parallel Processing. Portland, Oregon, USA, Septiembre 8-12, 2008 C. Acosta, F. J. Cazorla, A. Ramírez and M. Valero
  • Dissecting Transactional Executions in Haskell Second ACM Workshop on Transactional Computing TRANSACT - Agosto 2008 C. Perfumo, N. Sonmez, O. Unsal, A. Cristal, T. Harris and M. Valero
  • The MPI+SMPSs Programming Model ACACES 2008, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 16th. Academia Press, ISBN 978 90 382 1288 3 ,pp.41-45 V. Marjanovic, J. M. Pérez, J. Labarta and M. Valero
  • Scalability of Macroblock-level Parallelism for H.264 Decoding ACACES 2008, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 16th. Academia Press, ISBN 978 90 382 1288 3 pp. 59-63 M. Alvarez, A. Ramírez, X. Martorell, E. Ayguadé and M. Valero
  • Transactional Look-based Parallel Program ACACES 2008, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 16th. Academia Press, ISBN 978 90 382 1288 3 pp. 71-75 G. Kestor, O. Unsal, A. Cristal and M. Valero
  • Profiling Transactional Memory Applications on an Atomic Block Basis ACACES 2008, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 16th. Academia Press, ISBN 978 90 382 1288 3, pp 75-79 N. Sonmez, C. Perfumo, S. Stipic, A. Cristal, O. Unsal and M. Valero
  • Parallelization Strategies for Smth-Watermann Algorithm in a Cell BE ACACES 2008, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 16. Academia Press, ISBN 978 90 382 1288 3, pp. 147-151 F. Sánchez, A. Ramirez and M. Valero
  • 3D Die-Stacking Architectures: State of the Art ACACES 2008, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 16. Academia Press, ISBN 978 90 382 1288 3, pp. 203-207 A. J. Vega, A. Ramírez and M. Valero
  • Understanding the Overhead of the Spin-lock Loop in CMT Architectures WIOSCA, 2008. Workshop on Intearction Between Operating Systems and Computer Architecture”. To be held in conjuction with ISCA 2008. Beijing, Junio 21-25, 2008 V. Cakarevic, P. Radojkovic, F. Cazorla, R. Gioiosa, A. Pajuelo, J. Verdu, M. Nemirosvky and M. Valero.
  • Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications SAMOS VIII: International Symposium on Systems, Architectures, Modelling and Simulation. Samos, Grecia, Julio 21-24, 2008 S. Isaza, F. Sanchez, G. Gaydadjiev, A. Ramirez and M. Valero
  • Towards fair, scalable, Locking EPHAM-2008. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods. Held with CGO-2008. Boston USA, Abril 6-8, 2008 E. Vallejo, S. Sanyal, T. Harris, M. Valero, O. Unsal, A. Cristal, F. Vallejo and R. Beivide
  • The Limits of Software Transactional Memory (STM): Dissecting Haskell STM Applications on a Many-Core Environment ACM, CF, Computing Frontiers. Ischia, Italia, Mayo 2008 C. Perfumo, N. Sönmez, S. Stipic, O. Unsal, A. Cristal, T. Harris and M. Valero
  • Nebelung: Execution Environment for Transactional OpenMP International Journal of Parallel Programming, 36(3): 326-346, Junio 2008 M. Milovanović, R. Ferrer, O. Unsal, A. Cristal, X. Martorell, E. Ayguadé, J. Labarta and M. Valero
  • Software-Controlled Priority Characterization of POWER5 Processor IEEE-ACM International Symposium on Computer Architecture. Beijing, Junio 21-25, 2008 C. Boneti, F. J. Cazorla, R. Gioiosa, M. Valero, A. Buyuktosunoglu and C-Y. Cher
  • A Two-level Load/Store Queue based on Execution Locality IEEE-ACM International Symposium on Computer Architecture. Beijing, Junio 21-25, 2008 M. Pericas, R. Gonzalez, F. J. Cazorla, A. Cristal, A. Veidenbaum, D. Jimenez and M. Valero
  • Evolucionary System for Prediction and Optimization of Hardware Architecture Performance IEEE Congress on Evolutionary Computation, CEC-2008. Hong Kong, Junio 1-6, 2008, pp. 1941-1948 P. A. Castillo, J. J. Merelo, M. Moreto, F. J. Cazorla, M. Valero, A. M. Mora, L. J. L. Laredo and S. A. McKee
  • Vectorized AES Core for High-Throughput Secure Environments VECPAR-2008. 8th International Meeting High Performance Computing for Computational Science, pp. 83-94. Toulouse, Francia, 24-27 Junio 2008 M. Pericas, R. Chaves, G. N. Gaydadjiev, S. Vassiliadis and M. Valero
  • Balancing HPC Applications Through Smart Allocation of Resources in MT Processors IPDPS-2008, The IEEE International Parallel& Distributed Procesing Symp0sium. Miami, Florida, Abril, 14-18, 2008 C. Boneti, F. J. Cazorla, J. Corbalán, R. Giogiosa, J. Labarta and M. Valero
  • Hybrid Transactional Memory to accelerate safe lock-based transactions TRANSACT. ACM Workshop on Transactional Computing. To be held in conjuction with PpoPP. Salt Lake, Febrero 23, 2008 E. Vallejo, T. Harris, A. Cristal, O. Unsal and M. Valero
  • Overlapping MPI Computation and Communication by Enforcing Speculative Dataflow INA-OCMC-08. Workshop on Interconnection Network Architectures On-Chip, Multi-Chip. To be held in conjuction with HiPEAC-2008, the +International Conference on High Performance Embedded Architectures and Compilers. Göteborg, Suecia, Enero 27-29, 2008 V. Subotic, J. Labarta and M. Valero
  • Runahead Threads to Improve SMT Performance HPCA-2008, The 14th IEEE International Symposium on High-Performance Computer Architecture. Salt Lake City, Feb, 16-20, 2008 T. Ramírez, A. Pajuelo, O. J. Santana and M. Valero
  • Architectural Performance Prediction using Evolutionary Artificial Neuronal Networks EvoWorkshops-2008. European Conference on Evolutionary Computation, Machine Learning and Data Mining in Bioinformatics. Napoli, Italia, 26-28, Marzo, 2008 P. A. Castillo, A. Mora, J. J. Merelo, J. L. J. Laredo, M. Moreto, F. J. Cazorla, M. Valero and S. A. McKee
  • Soft Real-Time Scheduling on SMT Processors with Explicit resource Allocation ARSC 2008, International Conference on Architecture and Computing Systems. Dresden, Alemania, Feb. 25-28, 2008 C. Boneti, F. J. Cazorla, R. Giogiosa and M. Valero
  • LPA: A First Approach to the Loop Processor Architecture HiPEAC 2008 Conference. International Conference on High Performance Embedded Architectures and Compilers. Göteborg, Suecia, Enero 27-29, 2008 A. Garcia, O. J. Santana, E. Fernandez, P. Medina, and M. Valero
  • MLP-Aware Dynamic Cache Partitioning HiPEAC 2008 Conference. International Conference on High Performance Embedded Architectures and Compilers. Göteborg, Suecia, Enero 27-29, 2008 M. Moreto, F. J. Cazorla, A. Ramirez, and M. Valero
  • Vectorized AES Code for High-Througput Secure Environmentes Workshop on “The Future of Computing”, Essays in Memory of Stamatis Vassiliadis, Delft, Septiembre 28th, 2007, pp. 91-100. ISBN: 978-90-807957-3-0 M. Pericás, R. Chaves, G. N. Gaydadjiev, S. Vassiliadis and M. Valero
  • HD-VideoBench: A Benchmark for Evaluating High Definition Digital Video Applications IISWC, IEEE Internacional Symposium on Workload Characterization. Boston, Septiembre 27-29, 2007 M. Alvarez, E. Salami, A. Ramírez and M. Valero
  • Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors OSHMA Workshop, Operating System Support for Heterogeneous Multicore Architectures”, to be held during PACT-2007 in Brasov, Romania, Septiembre 15-19, 2007 F. Zyulkyarov, O. Unsal, A. Cristal. M. Milovanovic, E. Ayguade, M. Valero and T. Harris
  • Multithreaded Software Transactional Memory and OpenMP MEDEA Workshop, Memory performance: Dealing with Applications, systemas and architecture”, held in conjunction wit PACT-2007 in Brasov, Romania, Septiembre 15-19, 2007 M. Milovanovic, R. Ferrer, V. Gajinov, O. Unsal, A. Cristal, E. Ayguade and M. Valero
  • Hardware Transactional Memory with Operating System Support: HTMOS HPCC Workshop, Highly Parallel Processing in a Chip, in conjunction with Euro-Par, Agosto 2007 S. Tomic, A. Cristal, O. Unsal and M. Valero
  • FAME: FAirly MEasuring Multithreaded Architectures IEEE-ACM PACT Conference, Parallel Architectures and Compilation Techniques. Brasov, Romania, Septiembre 15-19, 2007 J. Vera, F. J. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández and M. Valero
  • A Flexible Heterogeneous Multi-Core Architecture IEEE-ACM PACT Conference, Parallel Architectures and Compilation Techniques. Brasov, Romania, Septiembre 15-19, 2007 M. Pericas, R. González, A. Cristal, F. J. Cazorla, D. Jiménez and M. Valero
  • MLP-Aware Dynamic Cache Partitioning Poster. IEEE-ACM PACT Conference, Parallel Architectures and Compilation Techniques. Brasov, Romania, Septiembre 15-19, 2007 M. Moreto, F.J. Cazorla, A. Ramirez and M. Valero
  • Runahead Threads: Reducing Resource Contention in SMT Processors Poster. IEEE-ACM PACT Conference, Parallel Architectures and Compilation Techniques. Brasov, Romania, Septiembre 15-19, 2007 T. Ramirez, O. J. Santana, A. Pajuelo, and M. Valero
  • Seleccción del Banco de Registros y de la Política de Asignación de Registros en Procesadores SMT CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007 J. Alastruey, T. Monreal, F. J. Cazorla, V. Viñals and M. Valero
  • A New Proposal to Evaluate Multithreaded Processors CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007 J. Vera, F. J. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández and M. Valero
  • Introducing Runahead Threads for SMT Processors CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007 T. Ramírez, A. Pajuelo, O. J. Santana and M. Valero
  • Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007 I. González, M. Galluzzi, A. Cristal and M. Valero
  • El Procesador Kilo-Ruanahead, una Alternativa para Reducir el Número de Registros Físicos del Procesador Kilo-Instruction CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007E. Lara, A. Cristal and M. Valero
  • Reducing the Activity of Instruction Renaming in Loop Structures CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007 A. García, O. J. Santana, E. Fernéndez, P. Medina, A. Cristal and M. Valero
  • Online Prediction Throughput for Different Caches Sizes CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007 M. Moretó, F. J. Cazorla, A. Ramírez and M. Valero
  • Tolerant Region Reuse for Multimedia CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007 C. Alvarez, J. Corbal and M. Valero
  • Increasing the Performance of Haskell Software Transactional Memory CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007
  • Extending C/C++ Language with Atomic Constructs CEDI, Congreso de Informática Latina, Zaragoza, 11 al 14 de Septiembre de 2007 M. Milovanovic, O. Unsal, A. Cristal, S. Stipic, F. Zyulkyarov and M. Valero
  • Implicit Transactional Memory in Kilo-Instruction Multiprocessor Invited paper. ACSAC-2007. The Twelfth Asia-Pacific Computer Systems Architecture Conference. Seoul, Korea, Agosto 23-25, 2007. LNCS 4697, pp.339-353 M. Galluzzi, E. Vallejo, A. Cristal, F. Vallejo, R. Beivide, P. Stenstrom, J. Smith and M. Valero
  • Dissecting Transactional Executions in Haskell The Second ACM GIGPLAN Workshop on Transactional Computing. Portland, Oregon, Agosto 16, 2007 C. Perfumo, N. Sonmez, O. Unsal, A. Cristal and M. Valero
  • Transactional Memory and openMP ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 18. Academia Press, ISBN 978 90 382 1127 5, pp.151 M. Milovanovic, R. Ferrer, O. Unsal, A. Cristal, X. Martorell, E. Ayguade, J. Labarta and M. Valero
  • Development and Analysis of the Haskell Transactional Memory Benchmark Suite ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 18. Academia Press, ISBN 978 90 382 1127 5, pp. 139-140 C. Perfumo, N. Sonmez, A. Cristal, O. Unsal and M. Valero
  • Synthetic Workloads for Transactional Memory ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 18. Academia Press, ISBN 978 90 382 1127 5, pp. 135-137 F. Zyulkyarov, O. Unsal, A. Cristal and M. Valero
  • The Multi-State Processor ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 18. Academia Press, ISBN 978 90 382 1127 5, pp. 127-130 I. González, M. Galluzzi, A. Cristal and M. Valero
  • FAME: Evaluating Multithreaded Architectures ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 18. Academia Press, ISBN 978 90 382 1127 5, pp. 123-126 J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández and M. Valero
  • A First Glance at Runahead Threads ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 18. Academia Press, ISBN 978 90 382 1127 5, pp. 107-110 T. Ramirez, A. Pajuelo, O. J. Santana and M. Valero.
  • Parallelizing Deep Packet Processing in Highly Parallel Architectures ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 18. Academia Press, ISBN 978 90 382 1127 5, pp. 71-74 J. Verdu, M. Nemirovsky and M. Valero
  • Improving Performance of MPI Applications using Speculative Communication ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 18. Academia Press, ISBN 978 90 382 1127 5, pp.69-70 V. Subotic, V. Marjanovic, J. Labarta and M. Valero
  • Transactional Memory and OpenMP In International Workshop on OpenMP, Juny 2007.. In International Workshop on OpenMP, Junio 2007 M. Milovanovic, R. Ferrer, O. Unsal, A. Cristal, X. Martorell, E. Ayguadé, J. Labarta and M. Valero
  • OpenMP and Transactional Memory IWOMP-07. International Workshop on OpenMP. Beijing, China,Junio 3-7, 2007 E. Ayguadé, M. Milovanovic, R. Ferrer, O. Unsal, A. Cristal, J. Labarta and M. Valero
  • On the Problem of Minimizing Workload Execution Time SAMOS, International Conference on Systems, Architectures, Modeling and Simulation. Samos/Grecia, Julio 16 - 19, 2007 F. J. Cazorla, E. Fernandez, R. Sakellariou, P. Knijnenburg and A. Ramírez
  • Online Prediction of Applications Cache Utility SAMOS, International Conference on Systems, Architectures, Modeling and Simulation. Samos/Grecia, Julio 16 - 19, 2007 M. Moretó, F. J. Cazorla, A. Ramírez and M. Valero
  • Compile time support for using Transactional Memory in C/C++ applications INTERACT-2007, 11th Annual Workshop on the Interaction between Compilers and Computer Architecture, Febrero 2007 M. Milovanovic, O. Unsal, A. Cristal, S. Stipic, F. Zyulkyarov and M. Valero
  • UnreadTVar: Extending Haskell Software Transactional Memory for Performance Eighth Symposium on Trends in Functional Programming, Abril 2007 C. Perfumo, N. Sonmez, S. Stipic, O. Unsal, A. Cristal and M. Valero
  • Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors CMP-MSI: Workshop on Chip Multiprocessor Memory Systems and Interconnects. In conjuction with HPCA 2007. Phoenix, Arizona, Febrero 2007 C. Acosta, F. J. Cazorla, A. Ramírez and M. Valero
  • Performance Impact of Unaligned memory Operations in SIMD Extensions for Video CODEC Applications ISPASS 2007. IEEE International Symposium on Performance Analysis of Systems and Software. San José, California, USA. Abril 25-27, 2007 M. Alvarez, E. Salami, J. Labarta and M. Valero
  • Performance Impact of the Interconnection Network on MareNostrum Applications HiPEAC Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, en Domingo, Enero 2007. Ghent, Bélgica, in conjunction with the HiPEAC’07 Conference A. Ramírez, O. Prat, J. Labarta and M. Valero
  • UnreadTVar: Extending Haskell Software Transactional Memory for Performance. Symposium on Trends in Functional Programming, 2007 - Abr 2007 N. Sonmez, C. Perfumo, S. Stipic, O. Unsal, A. Cristal and M. Valero
  • Microarchitectural Support for Speculative Register Renaming IPDPS07. IEEE International Parallel and Distributed Processing Sympsium. Long Beach, USA, Marzo 26-30, 2007 J. Alastruey, T. Monreal, V. Viñals and M. Valero
  • Measuring the Performance of Multithreaded Processors SPEC 2007 Benchmark Workshop. Austin, USA, Enero 2007 J. Vera, F. J. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández and M. Valero
  • Performance Analysis of Sequence Alignment Applications IISWC, IEEE Internacional Symposium on Workload Characterization. San José, USA, Octubre 2006 F. Sánchez, E. Salami, A. Ramírez and M.Valero
  • The Impact of Traffic Aggregation on the Memory Performance of Networking Applications Journal of Embedded Computing, pp. 77-82, Vol. 2, no. 1, Octubre 2006 J. Verdú, J. García, M. Nemirovsky and M. Valero
  • A Simple Speculative Load Control Mechanism for Energy Saving MEDEA Workshop: “MEmory performance:DEaling with Applications, systems and architecture”. Held in conjuction with PACT 2006 in Seattle, USA, Sept. 2006 T. Ramírez, M. Pajuelo, O. J. Santana and M. Valero
  • Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy IEEE ICCD Internation Conference on Computer Design. San Francisco, USA, Octubre 1-4, 2006 B. Slamat, D. Nicolaescu, A. Veidenbaum and M. Valero
  • Branch Predictor Guided Instruction Decoding IEEE PACT Parallel Architectures and Compiler Techniques. Seatle, Septiembre 2006 O. J Santana, A. Falcón, A. Ramírez and M. Valero
  • Implementando recuperaciones precisas en procesadores con consolidación fuera de orden XVII Jornadas de Paralelismo. Albacete, 18-20 Septiembre, 2006 I. González, O. J. Santana, A. Pajuelo, M. Valero
  • Improving EDF for SMT processors XVII Jornadas de Paralelismo. Albacete, 18-20 Septiembre, 2006 C. Boneti, F. J. Cazorla and M. Valero
  • Analysis of multithreading capabilities of current high-performance processors XVII Jornadas de Paralelismo. Albacete, 18-20 Septiembre, 2006 K. Kedzierski, F. J. Cazorla and M. Valero
  • Looking for novel ways to obtain fair measurements in multithreaded architectures XVII Jornadas de Paralelismo. Albacete, 18-20 Septiembre, 2006 J. Vera, F. J. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández and M. Valero
  • A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processor. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 26, pp. 9-11. Academia Press, ISBN 90 382 0981 9 I. González, O. J. Santana, A. Pajuelo and M. Valero
  • Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 26, pp. 113-116. Academia Press, ISBN 90 382 0981 9 K. Kedziersky, F. J. Cazorla and M. Valero
  • Boosting ILP&TLP with the Flexible Multi-Core (FMC) ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 26, pp. 125-128. Academia Press, ISBN 90 382 0981 9 M. Pericás, A. Cristal, R. González, F. J. Cazorla, D. A. Jiménez and M. Valero
  • Chip Multiprocessors with Implicit Transactions ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 26, pp. 167-170. Academia Press, ISBN 90 382 0981 9 E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J.E. Smith and M. Valero.
  • Reducing Simulation Time ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 26, pp. 233-236 Academia Press, ISBN 90 382 0981 9 M. Moreto, A. Ramírez and M. Valero.
  • A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures MoBS-2, Workshop on Modeling, Benchmarking and Simulation. In conjunction with ISCA. Bosaton, Junio 2006 J. Vera, F. J. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández and M. Valero
  • Speculative Early Register Release ACM International Conference on Computing Frontiers. Ischia, Mayo 2-5, 2006 J. Alastruey, T. Monreal, V. Viñals and M. Valero
  • Kilo-instruction Processors, Runahead and Prefetching ACM International Conference on Computing Frontiers. Ischia, Mayo 2-5, 2006 T. Ramírez, A. Pajuelo, O. J. Santana and M. Valero
  • A Decoupled Kilo-instruction Processor IEEE HPCA, International Conference on High Performance Computer Architecture. Austin, Febrero 2006 M. Pericás, R. González, A. Cristal, D. A. Jiménez and M. Valero
  • Performance Analysis of Sequence Alignment Applications In 2006 IEEE International Symposium on Workload Characterization , Enero 2006 F. Sánchez, E. Salamí, A. Ramírez and M. Valero
  • Parallel Processing in Biological Sequence Comparison using General Purpose Processors IISWC, IEEE Internacional Symposium on Workload Characterization. Austin, Texas, Octubre 6-7, 2005 F. Sánchez, E. Salami, M. A. Ramírez and M.Valero
  • A Performance Characterization of High Definition Digital Video Decoding Using H.264/AVC IISWC, IEEE Internacional Symposium on Workload Characterization. Austin, Texas, Octubre 6-7, 2005 M. Álvarez, E. Salami, M. A. Ramírez and M. Valero
  • Architectural Impact of Statefull Networking APPlications ANCS-2005. IEEE and ACM Symposium on Architectures for Networking and Communications Systems”. Princeton, New Jersey, Octubre 26-28, 2005 J. Verdú, M. Nemirovsky, J. García and M. Valero
  • Parallel Processing in Sequence Matching ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 25-29, pp. 279-282. Academic Press, ISBN 90 382 0802 2 F. Sánchez, E. Salami, A. Ramírez and M. Valero
  • A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 25-29, pp. 255-258. Academic Press, ISBN 90 382 0802 2 M. Álvarez, E. Salami, A. Ramírez and M. Valero
  • Hierarchical Gaussian Topologies ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 25-29, pp. 211-214. Academic Press, ISBN 90 382 0802 2 M. Moretó, C. Martínez, R. Beivide, E. Vallejo and M. Valero
  • Efficient Register File Management in High-ILP Processors ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 25-29, pp. 201-204. Academic Press, ISBN 90 382 0802 2 J. Alastruey, T. Monreal, V. Viñals and M. Valero
  • Quality of service for Simultaneous Multithreading Processors ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 25-29, pp. 67-70. Academic Press, ISBN 90 382 0802 2 F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellarious, E. Fernández, A. Ramírez and M. Valero
  • Different Approaches using Kilo-Instruction Processors ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 25-29, pp. 197-200. Academic Press, ISBN 90 382 0802 2 T. Ramírez, M. Galluzzi, A. Cristal and M. Valero
  • Overcoming the Memor Wall with D-KIPs ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 25-29, pp. 99-102. Academic Press, ISBN 90 382 0802 2 M. Pericás, R. González, A. Cristal and M. Valero
  • Complexity-Effectiveness in Multithreadind Architectures ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Láquila, Julio 25-29, pp. 79-82. Academic Press, ISBN 90 382 0802 2 C. Acosta, A. Falcón, A. Ramírez and M. Valero
  • Architectural Support for Real-TimeTask Scheduling in SMT Processors CASES 2005. International Conference on Compilers, Architecture and Synthesis for Embedded Systems. San José, Octubre 2005 F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellarious, E. Fernández, A. Ramírez and M. Valero
  • A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation Best paper Award. ICCD. IEEE International Conference on Computer Design. San José, USA, Octubre 2-5, 2005 A. Ramírez, A. Cristal, L. Villa, Alex V. Veidenbaum and M. Valero
  • Decoupled State-Execute Architecture ISHPC. International Symposium on High Performance Computers. Nara, Japón. Septiembre 7-9, 2005 M. Pericás, A. Cristal, R. González and M. Valero
  • Exploiting Instruction Locality with a Decoupled kilo-Instruction Processor ISHPC. International Symposium on High Performance Computers. Nara, Japón. Septiembre 7-9, 2005 M. Pericás, A. Cristal, R. González, D.A. Jiménez and M. Valero
  • Workload Characterization and Stateful Networking Aplications ISHPC. International Symposium on High Performance Computers. Nara, Japón. Septiembre 7-9, 2005 J. Verdú, M. Nemirovsky, J. García and M. Valero
  • Multiple Stream Prediction Best paper Award. ISHPC. International Symposium on High Performance Computers. Nara, Japón. Septiembre 7-9, 2005 O. J. Santana, A. Ramírez and M. Valero
  • KIMP: Multicheckpointing Multiprocessors XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith and M. Valero
  • Towards the Loop Processor Architecture XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 A. García, P. Medina, E. Fernández, O. J. Santana, A. Cristal and M. Valero
  • Predicting two Streams per Cycle XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 O. J. Santana, A. Ramírez and M. Valero
  • Metrics for the Evaluation of SMT Processors Performance XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 S. Mir, F. J. Cazorla, A. Ramírez and M. Valero
  • Eficacia versus Eficiencia: Una Decisión de Diseño en Runahead XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 T. Ramírez, A. Cristal, O. J. Santana, A. Pajuelo and M. Valero
  • Workload Analysis of Networking Applications XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 J. Verdu, M. Nemirosvky, J. García and M. Valero
  • Dynamically Controlled Resource Allocation in SMT XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 F. J. Cazorla, E. Fernández, A. Ramírez and M. Valero
  • Hierarchical Topologies for Large-Scale Two-Level Networks XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 M. Moreto, C. Martínez, E. Vallejo, M. Beivide and M. Valero
  • Arquitectura Simétrica Clusterizada basada en el Contenido XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 R. González, A. Cristal, M. Pericas, A. Veidenbaum and M. Valero
  • hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture XVI Jornadas de Paralelismo. Granada, 13-15 de Septiembre de 2005 C. Acosta, A. Falcón, M. A. Ramírez and M. Valero
  • Implementing Kilo-Instruction Multiprocessors Invited paper. IEEE Conference on Pervasive Services, ICPS-05. Santorini, Grecia. Julio 11-14, 2005 E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith and Mateo Valero
  • Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard In 2005 Advanced Computer Architecture and Compilation for Embedded Systems , Julio 2005 M. Alvarez, E. Salamí, M. A. Ramírez and M. Valero
  • Parallel Processing in Sequence Matching In 2005 Advanced Computer Architecture and Compilation for Embedded Systems, Julio 2005 F. Sánchez, E. Salamí, M. A. Ramírez and M. Valero
  • Complexity-Effectiveness in Multithreading Architectures In 2005 Advanced Computer Architecture and Compilation for Embedded Systems, Julio 2005 C. Acosta, A. Falcón, A. Ramírez and M. Valero
  • An Asymmetric Clustered Processor based on Value Content IEEE-ACM, International Conference on Supercomputing. Boston, USA, Junio 2005 R. González, A. Cristal, M. Pericás, A. Veidenbaum and M. Valero
  • A Vector-uSIMD-VLIW Architecture for Multimedia Applications ICPP, IEEE International Conference on Parallel Processing. Oslo, Noruega, Junio 4-7, 2005 E. Salami and M. Valero.
  • A Complexity-Effective Simultaneous Multithreading Architecture ICPP, IEEE International Conference on Parallel Processing. Oslo, Noruega, Junio 4-7, 2005 C. Acosta, A. Falcón, M. A. Ramírez and M. Valero
  • Control-Flow Independence Reuse via Dynamic Vectorization IPDPS05, IEEE-ACM 19th International Parallel and Distributed Processing Symposium. Denver, Colorado, 2005 A. Pajuelo, A. González and M. Valero
  • Effective Instruction Prefetching via Fetch Prestaging IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium. Denver, Colorado, 2005 A. Falcón, M. A. Ramírez and M. Valero
  • Performance Analysis of New Packet Trace Compression TCP Flow Clustering ISPASS05. IEEE International Symposium on Performance Analisys of Systems and Software. Austin, Texas, 2005 R. Holanda, J. Verdú, J. García and M. Valero
  • Architectural Impact of Stateful Networking Applications In 1st Symposium on Architecture for Networking and Communications Systems, Enero 2005 J. Verdú, J. García, M. Nemirovsky and M. Valero
  • On the scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications ISPASS05. IEEE International Symposium on Performance Analisys of Systems and Software. Austin, Texas, 2005 M. Alvárez, F. Sánchez, E. Salami, A. Ramírez and M. Valero
  • Implicit vs. Explicit Resouce Allocation in SMT Processors EUROMICRO Symposium on Digital System Design. (Ivited Paper). Rennes, Francia. Oct. 2004 F. J. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramírez and M. Valero
  • DCRA: Dynamically Controlled Resource Allocation in SMT Processors Micro-37. IEEE-ACM “International Symposium on Microarchitecture”. Portland, Dic. 4-8, 2004 F. J. Cazorla, A. Ramírez. E. Fernández and M. Valero
  • An Optimized Front-End Physical Register File with Banking and Writeback Filtering PACS´04. Workshop on Power-Aware Computer Systems. In conjuction with Micro-37. IEEE-ACM “International Symposium on Microarchitecture”. Portland, Dic. 4-8, 2004 M. Pericàs, R. González, A. Cristal, A. Veidenbaum and M. Valero
  • Speculative Execution for Hiding Memory Latency MEDEA Workshop: “MEmory performance:DEaling with Applications, systems and architecture”. Held in conjuction with PACT 2004 in Antibes, Francia. Sept. 2004 A. Pajuelo, A. González and M. Valero
  • Instruction Wakeup Mechanism: Power and Timing Evaluation CIC,s Research and Computing Science, series Octubre 2004; Mexico. City.ISBN:970-36-0194-4, ISSN:1665-9899 A. Ramírez, A. Cristal, L. Villa, Alex V. Veidenbaum and M. Valero
  • Traffic Aggregation Impact on the Memory Performance of Networking Applications MEDEA Workshop: “Memory performance:DEaling with Applications, systems and architecture”. Held in conjuction with PACT 2004 in Antibes, Francia. Sept. 2004 X. Verdú, M. Nemirosvky, J. García and M. Valero
  • Colas de Instrucciones Escalables y de Bajo Consumo para Procesadores Superescalares ENC2004. Encuentro Internacional de Ciencias de la Computación. Colima, Mexico, 20-24 de Septiembre de 2004 A. Ramírez, A. Cristal, A. Veidenbaum, L. Villa and M. Valero
  • Throughput versus Quality of Service in SMT processors Invited paper. Euromicro-DSD (Digital System Design). Rennes, Agosto-Septiembre 2004 F. J. Cazorla, A. Ramírez. E. Fernández, P. W. Knijnenburg, R. Sakellariou and M. Valero
  • Maintaining Thousands In-Flight Instructions Keynote paper. Europar Conference. LNCS. Pisa, Agosto-Septiembre, 2004
  • Enabling SMT for Real-Time Embedded Systems 12th European Signal Processing Conference (EUSIPCO). Vienna-Austria. Septiembre 2004 F. J. Cazorla, P. M.W. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramírez and M. Valero
  • Stream Predictor Guided Instruction Decoding XV Jornadas de Paralelismo. Almería. Septiembre 2004 O. J. Santana, A. Falcón, A. Ramírez and M. Valero
  • Selecting Where to Simulate SPEC2000 Using Streams Analysis XV Jornadas de Paralelismo. Almería. Septiembre 2004 A. Falcón, O. J. Santana, A. Ramírez and M. Valero
  • Analysis of Traffic Traces for Statefull Applications XV Jornadas de Paralelismo. Almería. Septiembre 2004 X. Verdú, J. García, M. Nemirovsky and M. Valero
  • Scalability and Complexity of 2-Dimensional SIMD Extensions XV Jornadas de Paralelismo. Almería. Septiembre 2004 M. Alvárez, F. Sánchez, E. Salami, A. Ramírez and M. Valero
  • Aggressive Speculative Execution for Hidding Memory Latency XV Jornadas de Paralelismo. Almería. Septiembre 2004 A. Pajuelo, A. González and M. Valero
  • Introducing Kilo-Instruction Multiprocessor XV Jornadas de Paralelismo. Almería. Septiembre 2004 M. Galluzzi, V. Puente. O. J. Santana, C. Acosta, A. Cristal, M. Beivide, J. A. Gregorio and M. Valero
  • Limits on Early Release of Physical Registers XV Jornadas de Paralelismo. Almería. Septiembre 2004 J. Alastruey, T. Monreal, V. Viñals and M. Valero
  • Heterogeneity-Aware Architectures XV Jornadas de Paralelismo. Almería. Septiembre 2004 C. Acosta, A. Falcón, A. Ramírez and M. Valero
  • Feasibility of QoS for SMT by Resource Allocation Euro-Par 2004. Pisa, Italia. Septiembre 2004 F. J. Cazorla, P. M.W. Knijnenburg, R. Sakellariou, E. Fernandez, A. Ramírez and M. Valero.
  • A Complexity-Effective Decoding Architecture Based on Instruction Streams WCED, Workshop on Complexity-Effective Design, in coordination with ISCA. Munich, Alemania, Junio 2004 O. J. Santana, A. Falcón, A. Ramírez, and M. Valero
  • Scalable Distributed Register File WCED, Workshop on Complexity-Effective Design in coordination with ISCA. Munich, Alemania, Junio 2004 R. Gonzalez, A. Cristal, M. Pericas, A. Veidenbaum and M. Valero
  • Friendly Threads: Smart Sharing of Resources in SMT Processors WCED, Workshop on Complexity-Effective Design in coordination with ISCA. Munich, Alemania, Junio 2004 F. J. Cazorla, E. Fernandez, A. Ramírez and M. Valero
  • Evaluating Kilo-instruction MultiProcessors Workshop WMPI in coordination with ISCA. Munich, Alemania, Junio 2004 M. Galluzzi, V. Puente, A. Cristal, R. Beivide. J.A. Gregorio and M. Valero
  • A Comprehensive Description of Kilo-instruction Processor CORE-2004. ISBN: 970-36-0149-9, pp. 144-154. National Conference on Computation. Mexico City, Mexico. Mayo 10, 2004 A. Cristal, O. J. Santana and M. Valero
  • Prophet-Critic Hybrid Branch Prediction ISCA-31. IEEE-ACM International Symposium on Computer Architecture. Munich, Alemania, Junio 2004 A. Falcon, J. Stack, A. Ramírez, K. Lai and M. Valero
  • A Content Aware Integer Register File Organisation ISCA-31. IEEE-ACM International Symposium on Computer Architecture. Munich, Alemania, Junio 2004 R. González, A. Cristal, D. Ortega, A.V. Veidenbaum and M. Valero
  • A Hybrid DRAM/SRAM Design for Fast Packet Buffers HPRS. IEEE Workshop on High Performance Switching and Routing, Phoenix, Arizona, Abril 18-20, 2004 J. García, M. March, L. Cerdá, J. Corbal and M. Valero
  • DCache Warn: an I-Fetch Policy To Increase SMT Efficiency IPDPS-04. International Parallel and Dystributed Processing Symposium. Santa Fe, New Mexico. Abril 26-30, 2004 F. J. Cazorla, E. Fernandez, A. Ramírez and M. Valero
  • A First Glance at Kilo-instruction Based Multiprocessors Invited paper to the session “The Memory Wall Problem”. CF‘04. ACM International Conference on Computing Frontiers. Ischia, Italia, Abril 12-14, 2004 M. Galluzzi, V. Puente, A. Cristal, R. Beivide. J.A. Gregorio and M. Valero
  • Predictable Performance in SMT processors CF‘04. ACM International Conference on Computing Frontiers. Ischia, Italia, Abril 12-14, 2004 F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramírez and M. Valero
  • Out-of-order Commit Processors HPCA-10. IEEE “International Conference on High-Performance Computer Architectures”. Madrid, España, Feb.14-18, 2004 A. Cristal, D. Ortega, J. Llosa and M. Valero
  • A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors HPCA-10. IEEE “International Conference on High-Performance Computer Architectures”. Madrid, España, Feb.14-18, 2004 A. Falcón, A. Ramírez and M. Valero
  • Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers WEPA-1: Workshop on Embedded Parallel Architectures at HPCA-10. Madrid, España, Feb. 14-18, 2004 M. March, J. García, Ll. Cerdá and M. Valero.
  • Analysis of Traffic Traces for Stateful Applications NP3 : Third Workshop on Network Processors and Applications at HPCA-10. Madrid, España, Feb. 14-18, 2004 J. Verdú, J. García, M. Nemirovsky and M. Valero
  • Direct Instruction Wakeup for OoO Procesors IWIA. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. Maui, Hawwaii, Enero 12-13, 2004 M. A. Ramírez, A. Cristal, A. V. Veidenbaum, L. Villa and M. Valero
  • Reducing Fetch Architecture Complexity Using Procedure Inlining INTERAC-8. Workshop on Interaction Between Computer Architecture and Compilers” at HPCA-10 Madrid, España, Feb. 14-18, 2004 O. J. Santana, A. Ramírez and M. Valero
  • Design and Implementation of High-Performance Memory Systems for Future Packet Buffers Micro-36 IEEE-ACM “International Symposium on Microarchitecture”. San Diego, Dic. 3-5, 2003 J. García, J. Corbal, Ll. Cerdá and M. Valero
  • A Fast Low Power Floating point Unit for Multimedia WASP-2. Workshop on Application Specific Processors. To be held in conjuction with Micro-36. San Diego, Dic.3-5, 2003 C. Álvarez, E. Salami, J. Corbal, J. R. A. Fonollosa and M. Valero
  • A Conflict-Free Memory Banking Architecture for Fast VOQ Packet Buffers IEEE GLOBECOM Conference. San Francisco, Diciembre 1-5, 2003 J. García, J. Corbal, Ll. Cerdá and M. Valero
  • Kilo-Instruction Processors Invited Paper. ISHPC-V. The 5th International Symposium on High Performance Computing. Tokyo, Japón, Octubre 20-22, 2003 A. Cristal, D. Ortega, J. Llosa and M. Valero
  • A Simple Low-Energy Instruction Wakeup Mechanism ISHPC-V. The 5th International Symposium on High Performance Computing. Tokyo, Japón, Octubre 20-22, 2003 A. Ramírez, A. Cristal, A. V. Veidenbaum, L. Villa and M. Valero
  • Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes ISHPC-V. The 5th International Symposium on High Performance Computing. Tokyo, Japón, Octubre 20-22, 2003 M. Pericas, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Tolerating Branch Predictor Latency on SMT Processors ISHPC-V. The 5th International Symposium on High Performance Computing. Tokyo, Japón, Octubre 20-22, 2003 A. Falcon, O. J. Santana, A. Ramírez and M. Valero
  • Improving Memory Latency Aware Fetch Policies for SMT Processors ISHPC-V. Best paper Award. The 5th International Symposium on High Performance Computing. Tokyo, Japón, Octubre 20-22, 2003 F. J. Cazorla, E. Fernández, A. Ramírez and M. Valero
  • A Case for Resource Conscious Out-of-Order Processor MEDEA Workshop: “MEmory performance:DEaling with Applications, systems and architecture”. Held in conjuction with PACT 2003 in New Orleans, Septiembre, 2003 A. Cristal, J. Martínez. J. Llosa and M. Valero.
  • A Low-Power-Instruction-Queue Wakeup Mechanism XIV Jornadas de Paralelismo. Madrid, Sept. 15-17, 2003 A. Ramírez, A. Cristal, A. Veindenbaum, L. Villa and M. Valero
  • A Dynamic Analysis of Instruction Streams XIV Jornadas de Paralelismo. Madrid, Sept. 15-17, 2003 O. J. Santana, M. Galluzzi, A. Ramírez and M. Valero
  • Arquitecturas Basadas en el Contenido XIV Jornadas de Paralelismo. Madrid, Sept. 15-17, 2003 R. González, A. Cristal, D. Ortega, and M. Valero
  • Dealing with Billions of Transistors XIV Jornadas de Paralelismo. Madrid, Sept. 15-17, 2003 C. Acosta, M. Galluzzi, S. Vajapeyam, A. Ramírez and M. Valero
  • Optimal Use of Registers in Aggressive Superscalar Processors XIV Jornadas de Paralelismo. Madrid, Sept. 15-17, 2003 A. Cristal, J. F. Martínez, J. Llosa and M. Valero
  • Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units 3rd Samos workshop on (Embedded) Systems, Architectures, Modeling, and Simulation. Samos, Julio 2003 M. Pericás, E. Ayguadé, J. Zalamea, J. Llosa, and M. Valero
  • Dynamic Memory Instruction Bypassing ICS-17, ACM “International Conference on Supercomputing”. San Francisco, Junio 23-26, 2003 D. Ortega, M. Valero and E. Ayguadé
  • CDE: A Compiler-Driven, Dependence-Centric, Eager-Execution Architecture for the Billion Transistor Area WECD. Workshop on Complexity-Effective Design. Held in conjunction with the 30th. ISCA Conference. San Diego, Junio 7, 2003 C. Acosta, S. Vajapeyam, A. Ramírez and M. Valero
  • Hierarchical Clustered Register File Organization for VLIW Processors IPDPS-2003. International Parallel and Distributed Processing Symposium. Nice, Francia, Abril 2003 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • An MPEG-4 Performance Study for non-SIMD General Purpose Architectures ISPASS-2003. IEEE International Symposium on Performance Analysis of Systems and Software. Marzo 6-8, 2003, Austin, Texas, USA S. A. McKee, Z. Fang and M. Valero
  • Latency Tolerant Branch Predictors IWIA: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. Maui, Hawwaii, Enero 12-13, 2003, pp. 30-39 O. J. Santana, A. Ramírez and M. Valero
  • Fetching Instruction Streams Micro-35 IEEE-ACM “International Symposium on Microarchitecture”. Istanbul, Turquía Nov, 18-22. 2002 A. Ramírez, O. J. Santana, J-L. Larriba and M. Valero
  • Three Dimensional Memory Vectorization for High Bandwidth Media Memory Systems Micro-35 IEEE-ACM “International Symposium on Microarchitecture”. Istanbul, Turquía, Nov, 18-22. 2002 J. Corbal, R. Espasa and M. Valero
  • Branch Clasification for SMT Fetch Gating MTEAC. Workshop on “Multithreaded Execution, Architecture and Compilation”. Micro-35. Istanbul, Noviembre 2002 P.M.W. Knijnenburg, A. Ramírez, J-L. Larriba and M. Valero
  • Cost Effective Memory Disambiguation for Multimedia Codes CASES 2002. International Conference on Compilers, Architecture and Synthesis for Embedded Systems. Grenoble Octubre 7-9, 2002 E. Salami, C. Álvarez, J. Corbal and M. Valero
  • Cost-Effective Compiler Directed Memory Prefetching and Bypassing PACT´02. IEEE “Parallel Architectures and Compiler Techniques”. Charlottesville, Virginia, Septiembre 22-25, 2002 D. Ortega, E. Ayguadé, J-L Baer and M. Valero
  • Análisis y Caracterización de los Bucles XIII Jornadas de Paralelismo. Lleida, Sept. 9-11, 2002 A. García, E. Fernández, P. Medina, A. Ramírez and M. Valero
  • Retos en el Diseño de Nertwork Processors XIII Jornadas de Paralelismo. Lleida, Sept. 9-11, 2002 J. Verdú, J. Corbal, J. García and M. Valero
  • Vectorización Dinámica Especulativa XIII Jornadas de Paralelismo. Lleida, Sept. 9-11, 2002 A. Pajuelo, A. González and M. Valero
  • Estudio y Evaluación de Mecanismos de Control de la Especulación XIII Jornadas de Paralelismo. Lleida, Sept. 9-11, 2002 F. J. Cazorla, P. Medina, E. Fernández. A. Ramírez and M. Valero
  • ROBs Virtuales Utilizando Checkpoints XIII Jornadas de Paralelismo. Lleida, Sept. 9-11, 2002 A. Cristal and M. Valero
  • A Comparative Study of Redundancy in Trace Caches Europar Conference. Paderborn, Alemania, 27-30. Agosto, 2002 H.Vandierendonck, A. Ramírez, K. De Brosschere and M. Valero
  • Hardware Schemes for Early Register Release ICCP (International Conference on Parallel Processing). Vancouver, Britsh Colunbia, Canadá. Agosto 18-21, 2002 T. Monreal, V. Viñals, A. González and M. Valero
  • Investigating the Predictability of Linked Data Structures 6th WSEAS International Conference on Circuits. Crete, Julio, 7-14, 2002 B. Goeman, K. Bosschere and M. Valero
  • Speculative Dynamic Vectorization ISCA-29. IEEE-ACM International Symposium on Computer Architecture. Anchorage, Alaska. Mayo 25-29, 2002 A. Pajuelo, A. González and M. Valero
  • A Comprehensive Analysis of Indirect Branch Prediction ISHPC-IV. International Symposium on High Performance Computing. Nara, Japón. Octubre 2002 O. J. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramírez and M. Valero
  • Studying New Ways for Improving Adaptive History Length Branch Predictors ISHPC-IV. International Symposium on High Performance Computing. Nara, Japón. Octubre 2002 A. Falcón, O. J. Santana, P. Medina, E. Fernández, A. Ramírez and M. Valero.
  • Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures IWIA’02. Kohala Coast, Big Island, Hawaii, Enero 10-11, 2002, pp 67- 76 P. M. W. Knijnenburg, A. Ramírez, F. Latorre, J. Larriba, M. Valero
  • Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures Micro-34. IEEE-ACM “International Symposium on Microarchitecture”. Austin, Texas, USA, Diciembre 2-5. 2001 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • On the Efficiency of Reductions on Micro-SIMD Media Extensions PACT´01. IEEE “Parallel Architectures and Compiler Techniques”. Barcelona, España, Septiembre 2001 J. Corbal, R. Espasa and M. Valero
  • Fuzzy Memoization for Floating Point Multimedia Applications Work-in-Progress-Session. PACT´01. IEEE “Parallel Architectures and Compiler Techniques”. Best presentation Award. Barcelona, España, Septiembre 2001 C. Álvarez, J. Corbal, E. Salami and M. Valero
  • Performance Evaluation of Decoding and Dispatching Stages in Simultaneous Multithreaded Architectures SBAC-PAD 2001. Symposium on Computer Architecture and High Performance Computing. Pirenoplis, Brasil, Septiembre 2001 R. Goncalves, E. Ayguadé, M. Valero anD P. Navaux
  • An In-Depth Evaluation of the Multi-Stage Cascaded Predictor XII Jornadas de Paralelismo.Valencia, 3-4 Sept. 2001 O. J. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramírez and M. Valero
  • An Analysis of Dynamic History Length Fitting XII Jornadas de Paralelismo.Valencia, 3-4 Sept. 2001 A. Falcón, O. J. Santana, P. Medina, E. Fernández, A. Ramírez and M. Valero
  • MIRS: Modulo Scheduling with Integrated Register Spilling LCPC 2001. Workshop on Languages and Compilers for Parallel Computing. Kentucky, Agosto 1-3. 2001 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • Branch Prediction Using Profile Data Europar 2001. Manchester, Inglaterra, Sep. 2001 A. Ramírez, J. L. Larriba-Pey and M. Valero
  • Multimedia and Embedded Systems Europar 2001. Manchester, England, pp. 651-652 S. Vassiliadis, F. Catthoor, M. Valero and S. Cotofana
  • Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures IWACT. International Workshop on Advanced Compiler Technology for High Performance and Embedded Processors. ISBN 973-685-273-3. Bucharest, Romania, Julio 18-20. 2001 J. Zalamea, J. Llosa, E. Auguadé and M. Valero
  • On the Potential of Tolerant Region Reuse for Multimedia Applications ICS-15, ACM “International Conference on Supercomputing”. Sorrento, Naples, Italia. Junio 16-21, 2001 C. Álvarez, J. Corbal, Esther Salami and M. Valero
  • A Novel Register Renaming Mechanism that Boots Software Prefetching ICS-15, ACM “International Conference on Supercomputing”. Sorrento, Naples, Italia. Junio 16-21, 2001 D. Ortega, M. Valero and E. Ayguadé
  • A Cost Effective Architecture for Vectorizable Numerical and Multimedia Applications SPAA, ACM Symposium on Parallel Algorithms and Architectures. Julio 4-6, 2001. Crete, Grecia F. Quintana, J. Corbal, R. Espasa and M. Valero
  • Code Layout Optimizations for Transaction Processing Workloads ISCA-28, IEEE-ACM International Symposium on Computer Architecture. Göteborg, Suecia. Julio 2001 A. Ramírez, L. Barroso, K. Garachorloo, R. Cohen, J-Ll. Larriba, G. Lowney and M. Valero
  • Transistor Count and Chip-Space Estimation of SimpleScalar-based Microprocessor Model Workshop on Complexity-Effective Design. ISCA-28, IEEE-ACM International Symposium on Computer Architecture. Göteborg, Suecia. Julio 2001 M. Steinhaus, R. Kolla, J. Larriba-Pey, T. Ungerer and M. Valero
  • Future High-Performance Microprocessors ASCI-2001. Advenced School for Computing and Imaging. Heijen Países Bajos, Mayo 30- Junio 1, 2001, pp.13-14 M. Valero
  • DLP+ TLP Processors for the Next Generation of Media Workloads HPCA-7. IEEE “International Conference on High-Performance Computer Architectures”. Monterrey, Mexico. Enero, 2001 J. Corbal, R. Espasa and M. Valero
  • Two-level Hierarchical Register File Optimization for VLIW Processors Micro-33. IEEE-ACM “International Symposium on Microarchitecture”,. Monterey, USA, Noviembre 2000 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • Computación de Altas Prestaciones: Arquitecturas, Compiladores, Herramientas, Sistemas Operativos y Algoritmos I Seminario del Programa Nacional de Tecnologías de la Información y de las Comunicaciones”. Almagro, Ciudad Real. Septiembre, 25-26 del 2000 M. Valero and V. Viñals
  • Architectures for one Billion of Transistors IEEE-ACM International Symposium on System & Synthesis. Madrid, Sept. 20-22, 2000. IEEE Computer Society Press, ISBN 0-7695-0765-4 M. Valero
  • Parallel Computer Architecture: Introduction to the Topic Lectures Notes in Computer Science number 1900. Springer. Pp 537-538, Agosto 2000 S. Müller, P. Stenström, M. Valero and S. Vassiliadis
  • The Effect of Code Reordering on Branch Prediction PACT´00. IEEE “Parallel Architectures and Compiler Techniques”. Philadelphia, USA, Octubre 2000 A. Ramírez, J. L. Larriba-Pey and M. Valero
  • A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies SBAC-PAD 2000. Symposium on Computer Architecture and High Performance Computing. Sao Paolo, Brasil, Octubre 2000 R. Goncalves, E. Ayguadé, M. Valero and P. Navaux
  • Performance Analysis of a Feasible Superscalar+ Vector Architecture XI Jornadas de Paralelismo. Granada, 11-13 de Septiembre del 2000 F. Quintana, R. Espasa and M. Valero
  • Liberacion Anticipada de Registros XI Jornadas de Paralelismo. Granada, 11-13 de Septiembre del 2000 T. Monreal, A. González, V. Viñals and M. Valero
  • On the Perfornance of Fetch Engines Running DSS Workloads Europar-2000, Munich, Agosto 2000 C. Navarro, A. Ramírez, J. L. Larriba-Pey, Mateo Valero
  • Multiple-Banked Register File Architecture ISCA-27, IEEE-ACM International Symposium on Computer Architecture. Vancouver, Junio 2000 J. L. Cruz, A. González and M. Valero
  • Improved Spill Code Generation for Software Pipelined Loops PLDI, ACM “Programming Language Design and Implementation”. Vancouver, Junio 2000 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • The Stream Processor Work-in-progress Session. HPCA-6. IEEE “International Symposium on High-Performance Computer Architecture”. Toulouse, Francia. 10-12 Enero 2000 A. Ramírez, J. L. Larriba-Pey and M. Valero
  • Semi-Static Branch Prediction for Optimized Code Layouts Third Workshop on Computer Architecture Evaluation using commercial Workloads. HPCA-6. IEEE “International Symposium on High-Performance Computer Architecture”. Toulouse, Enero 2000 A. Ramírez, J. L. Larriba-Pey and M. Valero
  • Fetch Engines and Databases Third Workshop on Computer Architecture Evaluation using commercial Workloads. HPCA-6. IEEE “International Symposium on High-Performance Computer Architecture”. Toulouse, 10-12 Enero 2000 C. Navarro, A. Ramírez, J. L. Larriba-Pey and M. Valero
  • Trace Cache Redundancy: Blue and Red Traces HPCA-6. IEEE “International Symposium on High-Performance Computer Architecture”. Toulouse, Enero 2000 A. Ramirez, J. L. Larriba-Pey and M. Valero
  • An Evolution of Different DLP Alternatives for the Embedded Multimedia Domain MP-DSP 1st Workshop on Media Processors and DSP´s. 15 Noviembre 1999. Haifa, Israel J. Corbal, E. Salami, R. Espasa and M. Valero
  • Exploiting a New Level of DLP in Multimedia Applications Micro-32. IEEE-ACM “International Symposium on Microarchitecture”. Haifa, Israel, 16-18 Noviembre 1999 J. Corbal, R. Espasa, M. Valero
  • Delaying Physical Register Allocation Through Virtual-Physical Registers Micro-32. IEEE-ACM “International Symposium on Microarchitecture”. Haifa, Israel, 16-18 Noviembre 1999 T. Monreal, A. González, M. Valero, J. González and V. Viñals
  • MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications SC´99 “Supercomputing Conference” Oregon, Noviembre 1999 J. Corbal, R. Espasa and M. Valero
  • A Characterization of Parallel SPECint Programs in Simultaneous Multithreading Architectures PACT´99. IEEE “Parallel Architectures and Compiler Techniques”. New Beach, 12-16 Octubre 1999 D. Ortega, I. Martel, E. Ayguadé, M. Valero and V. Venkat
  • Impact on Performance of Fused Multiply-Add Units in Agressive VLIW Architectures ICPP99. IEEE “International Conference on Parallel Processing”. Aizu-Wakamatsu, Fukushima, Japón, 21-24 Septiembre 1999 D. López, J. Llosa, E. Ayguadé and M. Valero
  • Code reordering of decission support systems for optimized instruction fetch ICPP99. IEEE “International Conference on Parallel Processing”. Aizu-Wakamatsu, Fukushima, Japón, 21-24 Septiembre, 1999 A. Ramírez, J. L. Larriba, C. Navarro, X. Serrano, J. Torrellas and M. Valero
  • A Register File Cache X Jornadas de Paralelismo. La Manga del Mar Menor (Murcia), 13-15 Septiembre de 1999 J. L. Cruz, A. González, M. Valero, N. Topham
  • Trace Cache Redundancy X Jornadas de Paralelismo. La Manga del Mar Menor (Murcia), 13-15 Septiembre de 1999 A. Ramírez, J. LL. Larriba-Pey, M. Valero
  • A Characterisation of Parallel SPECint Programs in Processor Multi-Threading Architectures X Jornadas de Paralelismo. La Manga del Mar Menor (Murcia), 13-15 Septiembre de 1999 D. Ortega, I. Martel, V. Krishnan, E. Ayguadé and M. Valero
  • Memory Controlled Spill Code for Software Pipelining X Jornadas de Paralelismo. La Manga del Mar Menor (Murcia), 13-15 Septiembre de 1999 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • Instruction Level Parallelism and Uniprocessor Architecture EuroPar 99. Lectures Notes in Computer Science nº 1685. Editorial Springer-Verlag. Tolousse, Francia, 1-3 Septiembre 1999, pp. 1241-1242
    P. Sainrat and M. Valero
  • Software Trace Cache ICS-13. ACM “International Conference on Supercomputing” (ICS-99). Seleccionado uno de los mejores 35 artículos durante estos 25 últimos años de Conferencia.
    Rhodes, Junio 1999, pp. 119-126 A. Ramírez, J. L. Larriba, C. Navarro, J. Torrellas and M. Valero
  • Adding a Vector Unit to a Superscalar Processor ICS-13. ACM “International Conference on Supercomputing”. Rhodes (Grecia), Junio 1999, pp. 1-10 F. Quintana, J. Corbal, R. Espasa and M. Valero
  • Increasing Effective IPC by Exploiting Distant Parallelism ICS-13. ACM “Int. Conference on Supercomputing”. Rhodes, Junio 1999, pp. 348-355 I. Martel, D. Ortega, E. Ayguadé and M. Valero
  • Optimizing Instruction Fetch for Decision Support Workloads Second Workshop on Computer Architecture Evaluation using Commercial Workloads. HPCA-5. IEEE “International Symposium on High Performance Computer Architecture”. Orlando, Enero 10, 1999 A. Ramírez, J. L. Larriba, C. Navarro, X. Serrano, J. Torrellas and M. Valero
  • Widening resources: a cost-effective technique for aggressive ILP architectures Micro-31. IEEE-ACM “International Symposium on Microarchitecture”, pp. 237-246. Dallas, Texas, 30 Noviembre – 2 Diciembre 1998 D. López, J. Llosa, E. Ayguadé and M. Valero
  • Widening resources: a cost-effective technique for aggressive ILP architectures IX Jornadas de Paralelismo, pp. 243-250. Donostia, 2-4 de Sept. de 1998 D. López, J. Llosa, E. Ayguadé and M. Valero
  • Command Vector Memory Systems: High Performance at low cost IX Jornadas de Paralelismo, pp. 299-306. Donostia, 2-4 de Septiembre de 1998 J. Corbal, R. Espasa and M. Valero
  • Command-Vector Memory System PACT’98. IEEE “Parallel Architectures and Compilation Techniques”. Paris, Noviembre 1998 J. Corbal, R. Espasa and M. Valero
  • A Performance Study of Out-of-order Vector Architectures and Short Registers pp. 37-44. ICS-12. ACM “International Conference on Supercomputing” (ICS-98). Melbourne, 12-17 Julio 1998 L. Villa, R. Espasa and M. Valero
  • Vector Architectures: Past, Present and Future pp. 425-432. ICS-12. ACM “International Conference on Supercomputing” (ICS-98). Melbourne, 12-17 Julio 1998 M. Valero, R. Espasa and J. E. Smith
  • Resource Widening Versus Replication: Limits and Performance – Cost Trade-Off pp. 441-448. ICS-12. ACM “International Conference on Supercomputing” (ICS-98). Melbourne, 12-17 Julio 1998 D. López, J. Llosa, M. Valero and E. Ayguadé
  • Registers Size Influence on Vector Architectures pp. 495-506 VECPAR-98. International Meeting on Vector and Parallel Processing. Porto, Portugal, Junio 1998 L. Villa, R. Espasa and M. Valero
  • A comparison between superescalar and vector processors pp. 439-452. VECPAR-98. International Meeting on Vector and Parallel Processing. Porto, Junio 1998 F. Quintana, R. Espasa and M. Valero
  • Rendimiento de una Cache escalar en una arquitectura vectorial fuera de orden CONIELECOMP-98. VIII Congreso Internacional de Electrónica, Comunicaciones y Computadores. Choluba, Puebla, México, Febrero 1998 L. Villa, R. Espasa and M. Valero
  • Virtual-Physical Registers HPCA-4. IEEE “International Symposium on High-Performance Computer Architecture”. Las Vegas (Nevada), 1-4 Febrero 1998 A. González, J. González and M. Valero
  • Interconnection Networks Introducción a la Sesión PDP98 “Parallel and Distributed Processing”. Madrid, 21-23 Enero 1998 M. Valero
  • Effective use of Vector Registers in Decoupled Vector Architectures PDP-98 “Euromicro Workshop on Parallel and Distributed Processing”. Madrid, 21-23 de Enero, 1998 L. Villa, R. Espasa and M. Valero
  • A case for merging the ILP and DLP paradigms PDP-98 “Euromicro Workshop on Parallel and Distributed Processing”. Madrid, 21-23 de Enero, 1998 F. Quintana, R. Espasa and M. Valero
  • Simultanneous Multithreaded Vector Architecture Special Session on “Recent Advances in ILP Processor Architecture and Compiler Issues”. HiPC´97 “High Performance Computing Conference”. Bangalore. India. 19-21 Diciembre 1997 R. Espasa and M. Valero
  • Virtual Registers Special Session on “Recent Advances in ILP Processor Architecture and Compiler Issues”. HiPC´97 “High Performance Computing Conference”. Bangalore. India. 19-21 Diciembre 1997 A. González, M. Valero, J. González and T. Monreal
  • Out-of-order Vector Architectures Micro-30. IEEE-ACM “International Symposium on Microarchitecture”. North Carolina, 1-3 Diciembre 1997 R. Espasa, M. Valero and J. E. Smith
  • Effective use of vector registers in Advanced Vector Architectures PACT-97. IEEE “Parallel Architectures and Compilation Techniques”. San Francisco, Noviembre 1997 L. Villa, R. Espasa and M. Valero
  • Static Locality Analysis for Cache Management PACT-97. IEEE “Parallel Architectures and Compilation Techniques”. San Francisco, 11-15 Noviembre 1997 J. Sánchez, A. González and M. Valero
  • A High Performance Vector Architecture for Future Billion of Transistor Processors INFOFEST-97. Budva, Montenegro. Septiembre 28-4 Octubre 1997 R. Espasa and M. Valero
  • A Victim Cache for Vector Registers ICS-11. ACM “International Conference on Supercomputing”. Vienna, Julio 1997 R. Espasa and M. Valero
  • Eliminating Cache Conflict Misses Through XOR-Based Placement Functions ICS-11. ACM “International Conference on Supercomputing”. Vienna, Julio 1997 A. González, M. Valero, N. Topham and J. M. Parcerisa
  • Increasing Memory Bandwidth with Wide Buses: Compiler, Architecture and Performance Tradeoffs ICS-11. ACM “International Conference on Supercomputing”. Vienna, Julio 1997 D. López, M. Valero, J. Llosa and E. Ayguadé
  • Multithreading Vector Architectures HPCA-3. IEEE “International Symposium on High-Performance Computer Architecture”, pp. 237-248. San Antonio, Febrero 1997 R. Espasa and M. Valero
  • Heuristics for Register-constrained Software Pipelining Micro-29. IEEE-ACM “International Symposium on Microachitecture”, pp. 250-261. Paris. Diciembre. 2-4 1996 J. Llosa, M. Valero and E. Ayguadé
  • Ictineo: A Tool for Research on ILP ACM “Supercomputing’96”. 17-22 Noviembre 1996 E. Ayguadé, C. Barrado, A. González, J. Labarta, D. Padua, J. Llosa, S. Moreno, D. López, F. J. Reig, M. Valero
  • Swing Modulo Scheduling: A Lifetime-Sensitive Approach PACT-96 “Parallel Architectures and Compilation Techniques”. Boston, Octubre 1996 J. Llosa, A. González, E. Ayguadé and M. Valero
  • Decoupled Vector Architectures HPCA-2. IEEE “International Symposium on High-Performance Computer Architecture”, pp. 281-290. San José (California), Febrero 3-7 1996 R. Espasa and M. Valero
  • Loop Parallelization: Revisiting Framework of Unimodular Transformations 4th Euromicro Workshop on Parallel and Distributed Processing. Braga (Portugal), Enero 24-26th 1996 J. Torres, E. Ayguadé, J. Labarta and M. Valero
  • Hypernode Reduction Modulo Scheduling Micro-28. IEEE-ACM “International Symposium on Microarchitecture”. Ann Arbor, Michigan (USA) Noviembre 29 - Diciembre 1 1995 J. Llosa, M. Valero, E. Ayguadé and A. González
  • Instruction Level Characterization of the Perfect Club Program on a Vector Computer XV International Conference of the Chilean Computer Science Society, pp. 198-209. Arica (Chile), Noviembre 1-3 1995 R. Espasa and M.Valero
  • A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality ICS-9. ACM “International Conference on Supercomputing”. Barcelona (España), Julio 3-7 1995 A. González, C. Aliagas and M. Valero
  • A proposal for Decoupled Vector Architectures Congreso APPARC-CSRD. Workshop. Barcelona, Julio 1995 R. Espasa and M. Valero
  • Decoupled Vector Architectures: A First Look VI Jornadas de Paralelismo. Barcelona, 2-3 Julio 1995 R. Espasa, M. Valero
  • ICTINEO: Una herramienta para la investigación en Paralelismo a Nivel de Instrucciones VI Jornadas de Paralelismo. 2-3 Julio 1995 E. Ayguadé, C. Barrado, J. Labarta, J. Llosa, D. López, S. Moreno, D. Padua, E. Riera, M. Valero
  • Vector Multiprocessors with Arbitrated Memory Access ISCA-22. IEEE-ACM “International Symposium on Computer Architecture”, pp 243-252. Santa Margherita Ligure (Italia), Junio 22-24 1995 M. Peiron, M. Valero, E. Ayguadé and T. Lang
  • Automatic Generation of Loop Scheduling for VLIW PACT-95. “Parallel Architectures and Compilation Techniques”. Crete (Grecia), Junio 1995 C. Barrado, J. Labarta, E. Ayguadé and M. Valero
  • Revisiting Framework of Linear Loop Transformations CPC-95 “Workshop on Compilers for Parallel Machines”. Málaga, Junio 26-30, 1995 J. Torres, E. Ayguadé, J. Labarta and M. Valero
  • Generation of a Periodic Pattern for VLIW CPC-95. “5th Workshop on Compilers for Parallel Machines”. Málaga (España), Junio 26-30 1995 C. Barrado, J. Labarta, E. Ayguadé and M. Valero
  • Bidirectional Scheduling to Minimize Register Requeriments CPC-95. “5th Workshop on Compilers for Parallel Machines”. Málaga (España), Junio 26-30 1995 J. Llosa, M. Valero and E. Ayguadé
  • Quantitative Analysis of Vector Code 3rd Euromicro Workshop on Parallel and Distributed Processing. Sanremo (Italia), Enero 25-27 1995 R. Espasa, M. Valero, D. Padua, M. Jiménez and E. Ayguadé
  • Non-consistent Dual Register Files to Reduce Register Pressure HPCA-1. IEEE “International Symposium on High Performance Computer Architecture”. North Carolina (USA), Enero 22-25 1995 J. Llosa, M. Valero and E. Ayguadé
  • Automatic Data Distribution: DDT V.2.0 ECUC´94 European Convex Users Conference. 18-21th Octubre 1994 E. Ayguadé, J. Labarta, J. García, M. Gironès, M. Valero
  • Register Requirement of Pipelined Loops and its Effects on Performance 2nd International Workshop on Massive Parallelism: Hardware, Software and Applications. Capri (Italia), Octubre 3-7 1994 J. Llosa, M. Valero, E. Ayguadé and J. Labarta
  • Detecting Affinity for Automatic Data Distribution 2nd International Workshop on Massive Parallelism: Hardware, Software and Applications. Capri (Italia), Octubre 3-7 1994 E. Ayguadé, J. Labarta, J. García, M. Gironès and M. Valero
  • Memory Access Synchronization in Vector Multiprocessors CONPAR 94-VAPP VI, pp. 414-425. Linz (Austria), 6-8 Septiembre 1994
    M. Valero, M. Peirón and E. Ayguadé
  • Using Sacks to Organize Registers in VLIW Machines CONPAR 94-VAPP VI, pp. 628-639. Linz (Austria), 6-8 Septiembre 1994
    J. Llosa, M. Valero, J. Fortes and E. Ayguadé
  • Detecting and Using Affinity in an Automatic Data Distribution Tool 7th Workshop on Programming Languages and Compilers for Parallel Computation. Ithaca (Nueva York), Agosto 1994
    E. Ayguadé, J. García, M. Gironés, J. Labarta, J. Torres and M. Valero
  • Synchronized Access to Streams in SIMD Vector Multiprocessors ICS-8. IEEE-ACM “International Conference on Supercomputing”. Manchester , Julio 11-15 1994 M. Peirón, M. Valero and E. Ayguadé
  • Access to Vectors in Multi-Module Memories 2nd Euromicro Workshop on Parallel and Distributed Processing. IEEE Computer Society Press, pp. 228-236. Málaga (España), Enero 26-28 1994 M. Valero, M. Peirón and E. Ayguadé
  • A Study of Data Sets and Affinity in the Perfect Club 4th International Workshop on Computers for Parallel Computers. Delft. Diciembre 1993 E. Ayguadé, J. Labarta, J. García, M. Gironès and M. Valero
  • Conflict-Free Access to Streams in Multiprocessor Systems 19th EUROMICRO Conference. Barcelona (Spain), Septiembre 6-9 1993 M. Peirón, M. Valero, E. Ayguadé and T. Lang
  • ALIGN and DISTRIBUTE-based linear Loop Transformations 6th Workshop on Programming Languages and Compilers for Parallel Computing. Portland (Oregon), Agosto 1993 J. Torres, E. Ayguadé, J. Labarta and M. Valero
  • Access to Streams in Multiprocessor Systems 1st Euromicro Workshop on Parallel and Distributed Processing. Gran Canaria, Enero 27-29, 1993 M. Valero, M. Peirón and E. Ayguadé
  • Partitioning the Iteration Space for Distributed- Memory Multiprocessors PACTA “International Conference on Parallel Computers and Transputer Applications”. Barcelona (España), Octubre 1992 J. Torres, E. Ayguadé, J. Labarta, M. Valero and J. M. Llabería
  • Conflict-Free Access of Vectors with Power-of-Two Strides ICS-6. IEEE-ACM “Intern. Conference on Supercomputing”, pp. 149-156. Washington, Julio 1992 M. Valero, T. Lang and E. Ayguadé
  • Increasing the Number of Strides for Conflict-Free Vector Access ISCA-19. IEEE-ACM “International Symposium on Computer Architecture”, Gold Coast, Australia, Mayo 1992 M. Valero, T. Lang, J. M. Llabería, M. Peiron, E. Ayguadé and J. J. Navarro
  • Architectural Tuning of the Cyclic Reduction Algorithm on vector Uniprocessors Jornadas de la Acción Especial sobre Paralelismo CICYT. Madrid (Spain), 23-25 Septiembre 1991 J. Lluis Larriba, M. Valero, J. J. Navarro and E. Herrada
  • Una Metodología para Paralelizar Bucles en Multiprocesadores con Memoria Distribuida Jornadas de la Acción Especial sobre Paralelismo. CICYT. Madrid (Spain), 23-25 Septiembre 1991 J. Torres, E. Ayguadé, J. Labarta, M. Valero, J. M. Llabería
  • Balanced Loop Partitioning using GTS 4th Workshop on Languages and Compilers for Parallel Computing. Santa Clara, Agosto 1991 J. Labarta, E. Ayguadé, J. Torres, M. Valero and J. M. Llabería
  • On Automatic Loop Data Mapping for Distributed-Memory Multiprocessors 2nd. European Distributed Memory Computers Conference. Munich (Alemania), Abril 1991 J. Torres, E. Ayguadé, J. Labarta, J. M. Llabería and M. Valero
  • Automatic Data Mapping for Distributed-Memory Multiprocessor System International Symposium Applied Informatics. Insbrück, Febrero 1991 J. Torres, E. Ayguadé, J. Labarta, J. M. Llabería and M. Valero
  • Implementation of Systolic Algorithms using Pipelined Functional Units ASAP-90. IEEE “Application Specific Array Processors Conference”, 1990. pp. 272-283 M. Valero-García, J. J. Navarro, J. M. Llabería and M. Valero
  • Nested-Loop Partitioning for Shared-Memory Multiprocessor Systems International Workshop on Compilers for Parallel Computers. París , Diciembre 1990 E. Ayguadé, J. Labarta, J. Torres, J. M. Llabería and M. Valero
  • Increasing Systolic Algorithms Granularity for Multicomputers Minisimposium “Linear Algebra in Systolic Arrays”. Second SIAM Conference on Linear Algebra. San Francisco (USA), Noviembre 3-5 1990 A. Fernández, J. M. Llabería, J. J. Navarro, M. Valero-García and M. Valero
  • Parallelism Evaluation and Partitioning of Nested Loops for Shared-Memory Multiprocessors 3rd. Workshop on Programming Languages and Compilers for Parallel Computing. Irvine-California, Agosto 1990 E. Ayguadé, J. Labarta, J. Torres, J. M. Llabería and M. Valero
  • LU Decomposition on a Mesh-Connected Transputer System Parallel Computing Action Workshop (ESPRIT). Southampton, Julio 9-10 1990 A. Fernández, J. M. Llabería, J. J. Navarro, M. Valero-García and M. Valero
  • Systematic Adaptation of Systolic Algorithms to the Hardware ISCA-16. IEEE-ACM “International Symposium on Computer Architecture”, Mayo 1989 M. Valero-García, J. J. Navarro, J. M. Llabería and M.Valero
  • On the use of Systolic Algorithms for Programming Distributed Memory Multiprocessors IEEE “Systolic Array Processor Conference”, pp. 631-640. Killarney (Irlanda).1989 A. Fernández, J. M. Llabería, J. J. Navarro, M. Valero-García and M. Valero
  • Two Optimal Static Systolic Arrays for the Algebraic Path Problem International Symposium on Mini and Microcomputer. Sant Feliu, Junio 1988 F. J. Núñez and M. Valero
  • Systematic Design of Two-Level Pipelined Systolic Arrays with Data Contraflow IEEE International Symposium on Circuits and Systems, pp. 2521-2525. Finlandia, Junio 1988 M. Valero-García, J.J. Navarro, J. M. Llabería and M. Valero
  • A Systolic Algorithm for the fast computation of the connected components of a graph IEEE International Symposium on Circuits and Systems. Finlandia, Junio 1988
  • F. J. Núñez and M. Valero
  • Arbitration Techniques of Packet Switching Multistage Interconnection Networks ICS-3. IEEE-ACM “International Conference on Supercomputing”. Boston, MA, Mayo 15-20 1988 J. Domingo, J. M. Llabería, M. Valero and J. Cortadella
  • Cost-Effectiveness of Multiplexed Multistage Interconnection Networks 6th. International Symposim of Applied Informatics. Grindelwald (Switzerland), February 1988 J. Domingo, J. M. Llabería and M. Valero
  • Optimal execution of the algebraic path problem in a bus-based multiprocessor with no arbitration mechanism 6th. International Symposium of Applied Informatics. Grindelwald (Suiza), Febrero 16-18 1988 F. J. Núñez and M. Valero
  • A Block Algorithm for the Algebraic Path Problem and its Execution on a Systolic Array IEEE “Systolic Arrays Processors Conference”, pp. 265-174. 1988 F. J. Núñez and M. Valero
  • Arbitration Methods increase the Throughput of Packed Switching Buffered Shuffle - Exchange Interconnection Networks 6th. International Symposium of Applied Informatics. Grindelwald (Suiza), Febrero 1988 J. Domingo, J. M. Llabería, J. Cortadella and M. Valero
  • LU Decomposition on a Linear Systolic Array Processors Fifth International Symposium Applied Informatics, 1987 J. J. Navarro, J. M. Llabería, F. J. Núñez and M. Valero
  • Particionado y Transformación DBT para la Resolución de Problemas Matriciales en Procesadores Sistólicos Seminario de Arquitectura y Tecnología de Computadores sobre Arquitecturas Multiprocesador y sus aplicaciones. Madrid, Enero, 1987 J. J. Navarro, J. M. Llabería, M. Valero
  • Efficient Mapping of Some Numerical Linear Algebra Problems on Systolic Array Processors Journées INRIA-IRISA, Rennes , Nov. 1986 pp 66-75 J. J. Navarro, J. M. Llabería, M. Valero, E. Herrada
  • Solving Matrix Problems With no Size Restriction on a Systolic Array Processor ICPP-86. IEEE “International Conference on Parallel Processing”, pp. 676-683. Chicago (USA), Agosto 1986 J.J. Navarro, J. M. Llabería and M. Valero
  • Computing Size-Independent Matrix Problems on Systolic Array Processors ISCA-13. IEEE-ACM “Intern. Symposium on Computer Architecture”, Tokyo, Japón, Mayo 1986 J. J. Navarro, J. M. Llabería and M. Valero
  • LU Decomposition With No Size-Restriction Using a One Dimensional Systolic Array Processor ICS-2. IEEE-ACM “International Conference on Supercomputing”, pp. 218-226. Santa Clara (USA), Mayo 1986 J. J. Navarro, J. M. Llabería, F. Núñez and M. Valero
  • Design Routing and Control of Two Optimal Bidirectional Networks ISMM “International Symposium on Mini and Microcomputer”. Sant Feliu, pp. 457-461. Junio 1985 J. R. Beivide, J. M. Llabería, J. L. Balcázar and M. Valero
  • Interconnection Networks with Two Unidirectional Multiplexed Busses for Multiprocessor Systems ISMM “International Symposium on Mini and Microcomputer”, Sant Feliu, Junio 1985 J. M. Llabería, M. Valero and E. Sanvicente
  • Analysis and Simulation of Multiplexed Single Bus Networks with and without Buffering ISCA-12. IEEE-ACM “International Symposium on Computer Architecture”, Mayo 1985 J. M. Llabería, M. Valero, J. Labarta and E. Herrada
  • Reducción de la Degradación y Conflicto en las Redes de Interconexión para Sistemas Multiprocesadores VI Congreso de la AEIA “Asociación Española de Informática y Automática” . Madrid (España), 1985, pp. 227-233 J. M. Llabería, J. Labarta, E. Herrada, M. Valero
  • Reduced Interconnection Networks Based in the Multiple-bus for Multiprocessor Systems MIMI-83 “Microprogramming and Microprocessing”, pp. 54-58. Lugano (Suiza), Junio 1983 M. A. Fiol, M. Valero, J. L. Andrés Yebra and T. Lang
  • A Performance Evaluation of the Multiple-Bus Network for Multiprocessor Systems ACM, SIGMETRICS 1983 M. Valero, E. Sanvicente, J. M. Llabería, T. Lang and J. Labarta
  • Some Improvements to the Shuffle Exchange-Networks for Multiprocessor Systems MIMI-83 “Microprogramming and Microprocessing”. Lugano (Suiza). Junio 1983 J. Labarta, M. Valero, J. M. Llabería, B. Bennassar, J. I. Navarro and E. Herrada
  • Performance Evaluation of Multiprocessor Systems with Private Caches and Multiple Bus Interconnection Network MIMI-83 “Microprogramming and Microprocessing”. San Francisco, Mayo 16-18 1983
    E. Herrada, J. Labarta, J. M. Llabería and M. Valero
  • An Algorithm to Minimize the Diameter of Directed Graphs SEIR-2, pp. 342-351. Santiago de Compostela (Spain), Septiembre 1982 J. L. Andrés, M.A. Fiol, M. Valero, I. Alegre and T. Lang
  • Evaluación de la Arquitectura Unibus con Memoria Local Distribuida SEIR-2, pp. 189-198. Santiago de Compostela (Spain), Septiembre 1982 E. Sanvicente, M. Valero, T. Lang
  • Evaluación de una Red de Interconexión tipo unibus trabajando en modo paquete SEIR-2, pp. 414-424. Santiago de Compostela , Sept. 1982 J. M. Llabería, M. Valero, E. Sanvicente, T. Lang, J. Labarta
  • Encaminamientos en Sistemas Multiprocesadores: Topologías Asociadas SEIR-2, pp. 209-223. Santiago de Compostela, Sept. 1982 M.A. Fiol, M. Valero, J. L. Andrés, T. Lang, E. Sanvicente
  • Modelos para evaluar las Redes de Interconexión Multibus y Multibus con Buses Parciales SEIR-2, pp. 324- 341. Santiago de Compostela , Sept. 1982 M. Valero, E. Sanvicente, T. Lang, J. M. Llabería
  • Performance Evaluation of the Crossbar Interconnection Network with Fast Memories pp. 28-31. MIMI-82 “Microprogramming and Microprocessing”. Cambridge (USA), Julio 7-9 1982 J. Labarta, M. Valero, E. Sanvicente, J. M. Llabería and T. Lang
  • Markov and Approximate Models for Multiple-bus and Multiple-bus with Partial Busses Interconnection Networks, pp. 32-36. MIMI-82. “Microprogramming and Microprocessing”. Cambridge, Julio 7-9, 1982.
  • Optimization of Double and Multiple-loop Structures for Local Networks MIMI-82 “Microprogramming and Microprocessing”. Cambridge (USA), Julio 1982 M.A. Fiol, M. Valero and J. L. Andrés Yebra
  • Approximate Model for Multiple-bus with Partial Busses Interconnection Networks Congreso Applied Modelling and Simulation (AMS’82). París (Francia). Junio 1982, pp. 12-16 M. Valero, E. Sanvicente, J. M. Llabería and T. Lang
  • Optimization of Double-loop Structures for Local Networks pp. 37-41. MIMI-82 “Microprogramming and Microprocessing”. París (Francia). Junio 1982 M.A. Fiol, M. Valero and J. L. Andrés Yebra
  • Exact and Approximate Models for Multiprocessor Systems with Single Bus and Distributed Memory MIMI-82 “Microprogramming and Microprocessing”, pp. 15-18. París (Francia). Junio 1982 E. Sanvicente, M. Valero, T. Lang and I. Alegre
  • Performance Evaluation of the Crossbar Interconnection Network with Fast Memories pp. 118-121. Congreso Applied Modelling and Simulation (AMS’82). París (Francia). Junio 1982 J. Labarta, M. Valero, E. Sanvicente, J. M. Llabería and T. Lang
  • Pasado, Presente y Futuro de la Arquitectura de los Microprocesadores Escuela de Informática de Verano. A.T.I. Barcelona, 14-18 de Septiembre de 1981, pp.23-47- M. Valero
  • Special Purpose Hardware for Signal Processing pp. c2/01 a c2/0/28. Invited paper. Workshop on signal processing and its applications. Vigo (España), Julio de 1981 T. Lang, M. Valero and J. Labarta
  • Mathematical Models to Evaluate the Memory Interference in Multimicrocomputer Systems pp. 21-26. Fifteen International Symposium on Mini and Microcomputers. México, 13-16 de Abril de 1981 M. Valero, I. Alegre and E. Sanvicente
  • Mecanismos de bajo nivel para comunicación en Redes Locales de Microcomputadores pp. 105-110. Fifteen International Symposium on Mini and Microcomputers. México. 13-16 de Abril de 1981 M. Valero and E. Herrada
  • Modelos Matemáticos para evaluar el Grado de Interferencia en el Acceso a Memoria Com en Sistemas Multimicroprocesadores XII Reunión Española sobre Estadística, Investigación Operativa e Informática. Jaca (Huesca), 24-26 Septiembre 1980 M. Valero and I. Alegre
  • Procesador de Comunicaciones para Redes Locales de Microcomputadores con Topología Multipunto XII Reunión Española sobre Estadística, Investigación Operativa e Informática. Jaca (Huesca), 24-26 Septiembre 1980 M. Valero and E. Herrada
  • Test para Memoria RAM de Semiconductores en Sistemas Microcomputadores Jornadas Técnicas de Electrónica Universidad-Empresa. Barcelona (Spain), Octubre 1979 E. Herrada, G. Pi and M. Valero
  • Diseño de un controlador de disco flexible con el WD1771 de Western Digital para MUBUS Jornadas Técnicas de Electrónica Universidad-Empresa. Barcelona (Spain), Octubre 1979 M. Valero
  • Top-down Methodology for I/O Systems Journées d’Electronique. Laussane (Suiza). pp. 129-140. Junio 1979 M. Medina and M. Valero